ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 101

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
ISP1761_4
Product data sheet
10.2 Endpoint description
If bit DMA_XFER_OK in the DMA Interrupt Reason register is asserted, it means that the
transfer counter has reached zero and the DMA transfer is successfully stopped.
If bit INT_EOT in the DMA Interrupt Reason register is set, it indicates that a short or
empty packet is received. This means that DMA transfer terminated. Normally, for an OUT
transfer, it means that remote host wishes to terminate the DMA transfer.
If both the bits DMA_XFER_OK and INT_EOT are set, it means that the transfer counter
reached zero and the last packet of the transfer is a short packet. Therefore, the DMA
transfer is successfully stopped.
Setting bit GDMA Stop in the DMA Command register (address: 0230h) will force the
DMA to stop and bit GDMA_STOP in the DMA Interrupt Reason register (address: 0250h)
will be set to indicate this event.
Setting bit Reset DMA in the DMA Command register (address: 0230h) will force the DMA
to stop and initialize the DMA core to its power-on reset state.
Each USB peripheral is logically composed of several independent endpoints. An
endpoint acts as a terminus of a communication flow between the USB host and the USB
peripheral. At design time, each endpoint is assigned a unique endpoint identifier; see
Table
enumeration), the endpoint number, and the transfer direction allows each endpoint to be
uniquely referenced.
The peripheral controller has 8 kB of internal FIFO memory, which is shared among the
enabled USB endpoints. The two control endpoints are fixed 64 bytes long. Any of the
seven IN and seven OUT endpoints can separately be enabled or disabled. The endpoint
type (interrupt, isochronous or bulk) and packet size of these endpoints can individually be
configured, depending on the requirements of the application. Optional double buffering
increases the data throughput of these data endpoints.
Table 96.
Endpoint
identifier
EP0SETUP
EP0RX
EP0TX
EP1RX
EP1TX
EP2RX
EP2TX
EP3RX
EP3TX
EP4RX
EP4TX
EP5RX
EP5TX
96. The combination of the peripheral address (given by the host during
Endpoint access and programmability
Maximum packet
size
8 bytes (fixed)
64 bytes (fixed)
64 bytes (fixed)
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
Rev. 04 — 5 March 2007
Double buffering Endpoint type
no
no
no
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
set-up token
control OUT
control IN
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
Hi-Speed USB OTG controller
© NXP B.V. 2007. All rights reserved.
Direction
OUT
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
ISP1761
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