ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 103

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
ISP1761_4
Product data sheet
10.4.2 ISP1761 DMA
10.4.3 ISP1761 peripheral suspend indication
10.4.4 ISP1761 interrupt and DMA common mode
10.5 Peripheral Controller-specific registers
For details on the DMA programming, refer to application note
DMA Initialization
In common mode, the interrupt and DMA signals of the Peripheral Controller are
redirected to pins that are used by the Host Controller because the Host Controller and
the Peripheral Controller share the same pins. Some control bits must be set in the HW
Mode Control register, see
Table 97.
Address Register
Initialization registers
0200h
020Ch
0210h
0212h
0214h
0300h
0374h
Data flow registers
022Ch
•
•
•
•
•
•
•
•
In 32-bit bus access mode, the register addresses are 4 bytes aligned. Therefore, the
DcBufferStatus register can be accessed using the upper-two bytes of the Buffer
Length register.
The SOFTCT bit in the Mode register has been removed. The DP_PULLUP control bit
in the OTG Control register is used in the ISP1761 in place of the SOFTCT bit in the
ISP1582.
Added the Interrupt Pulse Width register to define the pulse width of the interrupt
signal.
DMA mode 1 and DMA mode 2 in the ISP1582 are not supported in the ISP1761.
In DMA mode 0, counter mode is supported and external-EOT mode has been
removed.
Supports the 16-bit and 32-bit DMA. Does not support the 8-bit DMA.
The RD_N and WR_N signals are available for the DMA data strobe. These signals
are also used as data strobe signals during the PIO access. An internal multiplex will
redirect these signals to the DMA controller for the DMA transfer or to registers for the
PIO access.
A HIGH level on the DC_SUSPEND/WAKEUP_N pin indicates that the peripheral has
entered suspend mode. The pulse indication mode has been removed.
Address
Mode
Interrupt Configuration
Debug
DcInterruptEnable
HW Mode Control
OTG Control
Endpoint Index
Peripheral Controller-specific register overview
(AN10040)”.
Rev. 04 — 5 March 2007
Section
8.3.1.
Reset value
00h
0000h
FCh
0008h
0000 0000h
0000 0000h
0000 0086h
20h
Hi-Speed USB OTG controller
References
Section 10.5.1 on page 104
Section 10.5.2 on page 105
Section 10.5.3 on page 106
Section 10.5.4 on page 107
Section 10.5.5 on page 108
Section 8.3.1 on page 43
Section 9.5.2.1 on page 93
Section 10.6.1 on page 109
Ref. 7 “ISP1761 Peripheral
© NXP B.V. 2007. All rights reserved.
ISP1761
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