ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 109

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
ISP1761_4
Product data sheet
10.6.1 Endpoint Index register
10.6 Data flow registers
Table 108. DcInterruptEnable - Device Controller Interrupt Enable register (address 0214h)
The Endpoint Index register selects a target endpoint for register access by the
microcontroller. The register consists of 1 byte, and the bit allocation is shown in
Table
The following registers are indexed:
Bit
31 to 26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
•
•
•
•
Buffer Length
DcBufferStatus
Control Function
Data Port
109.
Symbol
-
EP7TX
EP7RX
EP6TX
EP6RX
EP5TX
EP5RX
EP4TX
EP4RX
EP3TX
EP3RX
EP2TX
EP2RX
EP1TX
IEP1RX
IEP0TX
IEP0RX
-
IEP0SETUP
IEVBUS
IEDMA
IEHS_STA
IERESM
IESUSP
IEPSOF
IESOF
IEBRST
bit description
Rev. 04 — 5 March 2007
Description
reserved
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the control IN endpoint 0.
Logic 1 enables interrupt from the control OUT endpoint 0.
reserved
Logic 1 enables interrupt for the set-up data received on endpoint 0.
Logic 1 enables interrupt for V
Logic 1 enables interrupt on detecting a DMA status change.
Logic 1 enables interrupt on detecting a high-speed status change.
Logic 1 enables interrupt on detecting a resume state.
Logic 1 enables interrupt on detecting a suspend state.
Logic 1 enables interrupt on detecting a pseudo SOF.
Logic 1 enables interrupt on detecting an SOF.
Logic 1 enables interrupt on detecting a bus reset.
BUS
sensing.
Hi-Speed USB OTG controller
© NXP B.V. 2007. All rights reserved.
ISP1761
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