ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 118

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
Table 127. DMA Transfer Counter register (address 0234h) bit allocation
Table 129. DcDMAConfiguration - Device Controller Direct Memory Access Configuration register (address 0238h)
ISP1761_4
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
bit allocation
10.7.3 DcDMAConfiguration register
R/W
15
0
0
R/W
R/W
R/W
R/W
31
23
15
0
0
0
0
0
0
7
0
0
Table 128. DMA Transfer Counter register (address 0234h) bit description
This register defines the DMA configuration for GDMA mode. The DcDMAConfiguration
register consists of 2 bytes. The bit allocation is given in
Bit
31 to 24
23 to 16
15 to 8
7 to 0
R/W
14
0
0
R/W
R/W
R/W
R/W
30
22
14
0
0
0
0
0
0
6
0
0
Symbol
DMACR4, DMACR[31:24]
DMACR3, DMACR[23:16]
DMACR2, DMACR[15:8]
DMACR1, DMACR[7:0]
R/W
13
0
0
R/W
R/W
R/W
R/W
29
21
13
0
0
0
0
0
0
5
0
0
Rev. 04 — 5 March 2007
DMACR4 = DMACR[31:24]
DMACR3 = DMACR[23:16]
DMACR2 = DMACR[15:8]
DMACR1 = DMACR[7:0]
R/W
12
R/W
R/W
R/W
R/W
0
0
28
20
12
0
0
0
0
0
0
4
0
0
reserved
Description
DMA Counter 4: DMA transfer counter byte 4
DMA Counter 3: DMA transfer counter byte 3
DMA Counter 2: DMA transfer counter byte 2
DMA Counter 1: DMA transfer counter byte 1
[1]
R/W
11
R/W
R/W
R/W
R/W
0
0
27
19
11
0
0
0
0
0
0
3
0
0
R/W
Table
R/W
R/W
R/W
R/W
10
0
0
26
18
10
Hi-Speed USB OTG controller
0
0
0
0
0
0
2
0
0
129.
R/W
R/W
R/W
R/W
R/W
25
17
9
0
0
0
0
0
0
9
0
0
1
0
0
© NXP B.V. 2007. All rights reserved.
ISP1761
118 of 163
R/W
R/W
R/W
R/W
R/W
24
16
8
0
0
0
0
0
0
8
0
0
0
0
0