ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 119

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
[1]
Table 131. DMA Hardware register (address 023Ch) bit allocation
[1]
ISP1761_4
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
The reserved bits should always be written with the reset value.
The reserved bits should always be written with the reset value.
10.7.4 DMA Hardware register
XFER_CNT
R/W
DIS_
R/W
7
0
0
7
0
0
Table 130. DcDMAConfiguration - Device Controller Direct Memory Access Configuration
The DMA Hardware register consists of 1 byte. The bit allocation is shown in
This register determines the polarity of bus control signals (DACK and DREQ).
Bit
15 to 8
7
6 to 4
3 to 2
1
0
R/W
R/W
6
0
0
6
0
0
reserved
Symbol
-
DIS_XFER_CNT
-
MODE[1:0]
-
WIDTH
register (address 0238h) bit description
reserved
[1]
R/W
R/W
5
0
0
5
0
0
Rev. 04 — 5 March 2007
[1]
Description
reserved
Disable Transfer Counter: Write logic 0 to perform DMA operation.
Logic 1 disables the DMA transfer counter (see
reserved
Mode:
00 — WR_N slave strobes data from the DMA bus into the
ISP1761; RD_N slave puts data from the ISP1761 on the DMA bus
01, 10, 11 — reserved
reserved
Width: This bit selects the DMA bus width for GDMA.
0 — 32-bit data bus
1 — 16-bit data bus
R/W
R/W
4
0
0
4
0
0
DACK_
R/W
POL
R/W
3
0
0
3
0
0
MODE[1:0]
DREQ_
POL
R/W
R/W
2
0
0
2
1
1
Hi-Speed USB OTG controller
reserved
R/W
R/W
1
0
0
1
0
0
Table
© NXP B.V. 2007. All rights reserved.
reserved
ISP1761
127).
Table
WIDTH
[1]
119 of 163
R/W
R/W
0
1
1
0
0
0
131.