ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 153

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
20. Revision history
Table 181. Revision history
ISP1761_4
Product data sheet
Document ID
ISP1761_4
Modifications:
ISP1761_3
Modifications:
Release date
20070305
20061127
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Globally changed from 32 kB
Section 7.5 “Phase-Locked Loop (PLL) clock
Table 52 “Power Down Control register (address 0354h) bit
31 to 16.
Table 113 “Control Function register (address 0228h) bit
and 2.
Section 10.6.3 “Data Port
Section 10.6.5 “DcBufferStatus
Section 10.7.4 “DMA Hardware
Table 155 “Recommended operating
Section 15.1.1.1 “Register or memory
Section 15.1.1.2 “Register
Section 15.1.1.3 “Register
Section 15.2.1.1 “PIO register read or
Section 15.2.1.2 “PIO register
The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
Changed OTG specification revision from 1.0a to 1.2.
Globally changed NrBytesTransferred[14:0] and NrBytesToTransfer[14:0] from 32 kB to 32 kB
Globally changed “Queue Head” to “Transfer Descriptor”.
Changed "Acknowledged Transfer List" to "Asynchronous Transfer List".
Table 2 “Pin description”: updated description for pins 3, 122 and 127.
Section 7.1 “ISP1761 internal architecture: advanced NXP slave Host Controller and hub”: updated
the remark.
Section 7.1.1 “Internal clock scheme and port selection”: updated the section title.
Section 7.2.2 “Structure of the ISP1761 Host Controller memory”: updated first sentence of the
second paragraph.
Section 7.3.1 “PIO mode access, memory read cycle”: updated the third bullet.
Section 7.5 “Phase-Locked Loop (PLL) clock multiplier”: updated the first paragraph.
Updated figure note for Figure 7 “ISP1761 power supply connection”, Figure 8 “Most commonly
used power supply connection” and Figure 9 “Hybrid mode”.
Section 7.8 “Overcurrent detection”: added a remark at the end of the paragraph.
Section 7.9 “Power-On Reset (POR)”: updated the first sentence.
Section 8.2.4 “FRINDEX register”: updated the first paragraph.
Section 8.3.6 “HcBufferStatus register”: added content.
Data sheet status
Product data sheet
Product data sheet
register”: updated the content.
Rev. 04 — 5 March 2007
read”: removed T
access”: added.
access”: added.
1 to 32 kB
register”: updated the second remark.
register”: changed bits 7 to 6 as reserved.
conditions”: added T
write”: removed T
write”: removed T
cy12
1 B.
multiplier”: updated the first paragraph.
.
Change notice
-
-
cy18
cy11
description”: updated description for bits 1
j
.
description”: updated description for bits
.
.
Hi-Speed USB OTG controller
Supersedes
ISP1761_3
ISP1761_2
© NXP B.V. 2007. All rights reserved.
ISP1761
153 of 163
1.