ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 158

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ISP1761ET

Manufacturer Part Number
ISP1761ET
Description
USB Interface IC USB 2.0 HS OTG HOST
Manufacturer
NXP Semiconductors
Datasheet

Specifications of ISP1761ET

Operating Supply Voltage
1.65 V to 3.6 V
Lead Free Status / Rohs Status
 Details
Other names
ISP1761ET,557

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NXP Semiconductors
Table 49. DMA Start Address register (address 0344h)
Table 50. DMA Start Address register (address 0344h)
Table 51. Power Down Control register (address 0354h)
Table 52. Power Down Control register (address 0354h)
Table 53. HcInterrupt - Host Controller Interrupt
Table 54. HcInterrupt - Host Controller Interrupt
Table 55. HcInterruptEnable - Host Controller
Table 56. HcInterruptEnable - Host Controller
Table 57. ISO IRQ Mask OR register (address 0318h)
Table 58. INT IRQ Mask OR register (address 031Ch)
Table 59. ATL IRQ Mask OR register (address 0320h)
Table 60. ISO IRQ Mask AND register (address 0324h)
Table 61. INT IRQ MASK AND register (address 0328h)
Table 62. ATL IRQ MASK AND register (address 032Ch)
Table 63. High-speed bulk IN and OUT: bit allocation . . .61
Table 64. High-speed bulk IN and OUT: bit description .62
Table 65. High-speed isochronous IN and OUT: bit
Table 66. High-speed isochronous IN and OUT: bit
Table 67. High-speed interrupt IN and OUT: bit
Table 68. High-speed interrupt IN and OUT: bit
Table 69. Microframe description . . . . . . . . . . . . . . . . . .72
Table 70. Start and complete split for bulk: bit allocation 73
Table 71. Start and complete split for bulk: bit
Table 72. SE description . . . . . . . . . . . . . . . . . . . . . . . . .76
Table 73. Start and complete split for isochronous: bit
Table 74. Start and complete split for isochronous: bit
ISP1761_4
Product data sheet
bit description . . . . . . . . . . . . . . . . . . . . . . . . .50
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .50
bit description . . . . . . . . . . . . . . . . . . . . . . . . .51
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .51
bit description . . . . . . . . . . . . . . . . . . . . . . . . .52
register (address 0310h) bit allocation . . . . . . .53
register (address 0310h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Interrupt Enable register (address 0314h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Interrupt Enable register (address 0314h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
bit description . . . . . . . . . . . . . . . . . . . . . . . . .57
bit description . . . . . . . . . . . . . . . . . . . . . . . . .57
bit description . . . . . . . . . . . . . . . . . . . . . . . . .58
bit description . . . . . . . . . . . . . . . . . . . . . . . . .58
bit description . . . . . . . . . . . . . . . . . . . . . . . . .58
bit description . . . . . . . . . . . . . . . . . . . . . . . . .58
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Rev. 04 — 5 March 2007
Table 75. Start and complete split for interrupt: bit
Table 76. Start and complete split for interrupt: bit
Table 77. Microframe description . . . . . . . . . . . . . . . . . . 84
Table 78. SE description . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 79. OTG Controller-specific register overview . . . . 91
Table 80. Address mapping of registers: 32-bit data
Table 81. Address mapping of registers: 16-bit data bus
Table 82. Vendor ID - Vendor Identifier (address
Table 83. Product ID - Product Identifier register
Table 84. OTG Control register (address set: 0374h,
Table 85. OTG Control register (address set: 0374h,
Table 86. OTG Status register (address 0378h) bit
Table 87. OTG Status register (address 0378h) bit
Table 88. OTG Interrupt Latch register (address set:
Table 89. OTG Interrupt Latch register (address set:
Table 90. OTG Interrupt Enable Fall register
Table 91. OTG Interrupt Enable Fall register
Table 92. OTG Interrupt Enable Rise register (address
Table 93. OTG Interrupt Enable Rise register (address
Table 94. OTG Timer register (address low word set:
Table 95. OTG Timer register (address low word set:
Table 96. Endpoint access and programmability . . . . . 101
Table 97. Peripheral Controller-specific register
Table 98. Address register (address 0200h) bit
Table 99. Address register (address 0200h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
0370h) register: bit description . . . . . . . . . . . . 92
(address 0372h) bit description . . . . . . . . . . . . 92
clear: 0376h) bit allocation . . . . . . . . . . . . . . . 93
clear: 0376h) bit description . . . . . . . . . . . . . . 93
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
037Ch, clear: 037Eh) bit allocation . . . . . . . . . 95
037Ch, clear: 037Eh) bit description . . . . . . . . 95
(address set: 0380h, clear: 0382h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
(address set: 0380h, clear: 0382h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
set: 0384h, clear: 0386h) bit allocation . . . . . . 96
set: 0384h, clear: 0386h) bit description . . . . . 97
0388h, low word clear: 038Ah; high word set:
038Ch, high word clear: 038Eh) bit allocation . 97
0388h, low word clear: 038Ah; high word set:
038Ch, high word clear: 038Eh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Hi-Speed USB OTG controller
© NXP B.V. 2007. All rights reserved.
ISP1761
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