ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 161

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
24. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. Adjusting analog overcurrent detection limit
Fig 11. Internal power-on reset timing . . . . . . . . . . . . . . .31
Fig 12. Clock with respect to the external power-on
Fig 13. NextPTD traversal rule. . . . . . . . . . . . . . . . . . . . .60
Fig 14. HNP sequence of events . . . . . . . . . . . . . . . . . . .87
Fig 15. Dual-role A-device state diagram. . . . . . . . . . . . .89
Fig 16. Dual-role B-device state diagram. . . . . . . . . . . . .90
Fig 17. Charge pump current versus voltage at
Fig 18. Charge pump current versus voltage at
Fig 19. USB source differential data-to-EOP transition
Fig 20. Register or memory write. . . . . . . . . . . . . . . . . .135
Fig 21. Register read . . . . . . . . . . . . . . . . . . . . . . . . . . .136
Fig 22. Register access . . . . . . . . . . . . . . . . . . . . . . . . .136
Fig 23. Memory read . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Fig 24. DMA read (single cycle). . . . . . . . . . . . . . . . . . .138
Fig 25. DMA write (single cycle) . . . . . . . . . . . . . . . . . .139
Fig 26. DMA read (multi-cycle burst) . . . . . . . . . . . . . . .140
Fig 27. DMA write (multi-cycle burst) . . . . . . . . . . . . . . .141
Fig 28. ISP1761 register access timing: separate
Fig 29. PIO register access . . . . . . . . . . . . . . . . . . . . . .143
Fig 30. DMA read or write . . . . . . . . . . . . . . . . . . . . . . .144
Fig 31. Package outline SOT425-1 (LQFP128) . . . . . . .146
Fig 32. Package outline SOT857-1 (TFBGA128). . . . . .147
Fig 33. Temperature profiles for large and small
ISP1761_4
Product data sheet
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin configuration (LQFP128); top view . . . . . . . . .6
Pin configuration (TFBGA128); top view . . . . . . . .6
Internal hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
ISP1761 clock scheme . . . . . . . . . . . . . . . . . . . .15
Memory segmentation and access block
diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
ISP1761 power supply connection. . . . . . . . . . . .27
Most commonly used power supply connection .28
Hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
(optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
various temperatures (worst case). . . . . . . . . . .132
various temperatures (typical case) . . . . . . . . . .132
skew and EOP width . . . . . . . . . . . . . . . . . . . . .134
address and data buses (8051 style). . . . . . . . .142
components . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
Rev. 04 — 5 March 2007
Hi-Speed USB OTG controller
© NXP B.V. 2007. All rights reserved.
ISP1761
continued >>
161 of 163