ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 46

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
Table 40.
[1]
ISP1761_4
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
HcDMAConfiguration - Host Controller Direct Memory Access Configuration register (address 0330h) bit
allocation
8.3.5 HcDMAConfiguration register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Table 39.
The bit allocation of the HcDMAConfiguration register is given in
Bit
31 to 2
1
0
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
reserved
SW Reset - Software Reset register (address 030Ch) bit description
Symbol
-
RESET_HC
RESET_ALL
[1]
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 04 — 5 March 2007
Description
reserved; write logic 0
Reset Host Controller: Reset only Host Controller-specific registers
(only registers with address below 300h).
0 — No reset
1 — Enable reset
Reset All: Reset all Host Controller and CPU interface registers.
0 — No reset
1 — Enable reset
DMA_COUNTER[23:16]
DMA_COUNTER[15:8]
DMA_COUNTER[7:0]
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
R/W
R/W
R/W
R/W
BURST_LEN[1:0]
27
19
11
0
0
0
3
0
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
Hi-Speed USB OTG controller
Table
ENABLE
_DMA
R/W
R/W
R/W
R/W
17
25
9
0
1
0
0
0
40.
© NXP B.V. 2007. All rights reserved.
ISP1761
DMA_READ_
WRITE_SEL
R/W
R/W
R/W
R/W
16
24
8
0
0
0
0
0
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