ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 48

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
[1]
Table 44.
ISP1761_4
Product data sheet
Bit
Symbol
Reset
Access
Bit
31 to 0
The reserved bits should always be written with the reset value.
Symbol
ATL_DONE_TIME
OUT[31:0]
ATL Done Timeout register (address 0338h) bit description
8.3.7 ATL Done Timeout register
8.3.8 Memory register
R/W
7
0
Table 43.
The bit description of the ATL Done Timeout register is given in
The Memory register contains the base memory read address and the respective bank.
This register needs to be set only before a first memory read cycle. Once written, the
address will be latched for the bank and will be incremented for every read of that bank
until a new address for that bank is written to change the address pointer.
The bit description of the register is given in
Bit
31 to 3
2
1
0
Access
R/W
R/W
6
0
Symbol
-
ISO_BUF_FILL ISO Buffer Filled:
INT_BUF_FILL
ATL_BUF_FILL ATL Buffer Filled:
HcBufferStatus - Host Controller Buffer Status register (address 0334h) bit
description
reserved
Value
0000 0000h ATL Done Timeout: This register determines the ATL done
R/W
5
0
[1]
Rev. 04 — 5 March 2007
Description
reserved
1 — Indicates one of the ISO PTDs is filled, and the ISO PTD area will
be processed.
0 — Indicates there is no PTD in this area. Therefore, processing of
ISO PTDs will be completely skipped.
INT Buffer Filled:
1 — Indicates one of the INT PTDs is filled, and the INT PTD area will
be processed.
0 — Indicates there is no PTD in this area. Therefore, processing of
INT PTDs will be completely skipped.
1 — Indicates one of the ATL PTDs is filled, and the ATL PTD area will
be processed.
0 — Indicates there is no PTD in this area. Therefore, processing of
ATL PTDs will be completely skipped.
Description
time-out interrupt. This register defines the time-out in milliseconds
after which the ISP1761 asserts the INT line, if enabled. It is
applicable to ATL done PTDs only.
R/W
4
0
R/W
0
3
Table
45.
ISO_BUF_
FILL
R/W
2
0
Hi-Speed USB OTG controller
Table
INT_BUF_
FILL
R/W
44.
1
0
© NXP B.V. 2007. All rights reserved.
ISP1761
ATL_BUF_F
R/W
ILL
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0
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