ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 56

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
[1]
ISP1761_4
Product data sheet
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
INT_IRQ_E
R/W
7
0
Table 56.
Bit
31 to 11 -
10
9
8
7
6
5
CLKREADY
R/W
_E
6
0
Symbol
OTG_IRQ_E
ISO_IRQ_E
ATL_IRQ_E
INT_IRQ_E
CLKREADY_E
HCSUSP_E
HcInterruptEnable - Host Controller Interrupt Enable register (address 0314h) bit
description
HCSUSP_
R/W
E
5
0
Rev. 04 — 5 March 2007
Description
reserved; write reset value
OTG_IRQ Enable: Controls the IRQ assertion because of events
present in the OTG Interrupt Latch register.
0 — No IRQ will be asserted
1 — IRQ will be asserted
For details, see
ISO IRQ Enable: Controls the IRQ assertion when one or more ISO
PTDs matching the ISO IRQ Mask AND or ISO IRQ Mask OR register
bits combination are completed.
0 — No IRQ will be asserted when ISO PTDs are completed
1 — IRQ will be asserted
For details, see
ATL IRQ Enable: Controls the IRQ assertion when one or more ATL
PTDs matching the ATL IRQ Mask AND or ATL IRQ Mask OR register
bits combination are completed.
0 — No IRQ will be asserted when ATL PTDs are completed
1 — IRQ will be asserted
For details, see
INT IRQ Enable: Controls the IRQ assertion when one or more INT
PTDs matching the INT IRQ Mask AND or INT IRQ Mask OR register
bits combination are completed.
0 — No IRQ will be asserted when INT PTDs are completed
1 — IRQ will be asserted
For details, see
Clock Ready Enable: Enables the IRQ assertion when internal clock
signals are running stable. Useful after wake-up.
0 — No IRQ will be generated after a CLKREADY_E event
1 — IRQ will be generated after a CLKREADY_E event
Host Controller Suspend Enable: Enables the IRQ generation when
the Host Controller enters suspend mode.
0 — No IRQ will be generated when the Host Controller enters
suspend mode
1 — IRQ will be generated when the Host Controller enters suspend
mode
reserved
R/W
4
0
[1]
Section
Section
Section
Section
DMAEOT
INT _E
R/W
3
0
7.4.
7.4.
7.4.
7.4.
reserved
R/W
2
0
Hi-Speed USB OTG controller
[1]
SOFITLINT
R/W
_E
1
0
© NXP B.V. 2007. All rights reserved.
ISP1761
reserved
R/W
56 of 163
0
0
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