ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 57

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
Table 57.
Table 58.
ISP1761_4
Product data sheet
Bit
31 to 0
Bit
31 to 0
Symbol
ISO_IRQ_MASK_
OR[31:0]
Symbol
INT_IRQ_MASK_
OR[31:0]
ISO IRQ Mask OR register (address 0318h) bit description
INT IRQ Mask OR register (address 031Ch) bit description
8.4.3 ISO IRQ MASK OR register
8.4.4 INT IRQ MASK OR register
8.4.5 ATL IRQ MASK OR register
Table 56.
Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a
hardware IRQ mask for each PTD done map. See
see
Each bit of this register (see
and is a hardware IRQ mask for each PTD done map. For details, see
Each bit of this register corresponds to one of the 32 ATL PTDs defined, and is a
hardware IRQ mask for each PTD done map. See
see
Bit
4
3
2
1
0
Section
Section
Access Value
R/W
Access Value
R/W
Symbol
-
DMAEOTINT_E DMA EOT Interrupt Enable: Controls assertion of IRQ on the DMA
-
SOFITLINT_E
-
HcInterruptEnable - Host Controller Interrupt Enable register (address 0314h) bit
description
7.4.
7.4.
0000 0000h
0000 0000h INT IRQ Mask OR: Represents a direct map for INT PTDs 31 to 0.
…continued
Rev. 04 — 5 March 2007
Description
reserved; write reset value
transfer completion.
0 — No IRQ will be generated when a DMA transfer is completed
1 — IRQ will be asserted when a DMA transfer is completed
reserved; write reset value
SOT ITL Interrupt Enable: Controls the IRQ generation at every SOF
occurrence.
0 — No IRQ will be generated on SOF occurrence
1 — IRQ will be asserted at every SOF
reserved; write reset value
Description
0 — No OR condition defined between INT PTDs 31 to 0.
1 — The bits corresponding to certain PTDs are set to logic 1 to
define a certain OR condition.
Description
ISO IRQ Mask OR: Represents a direct map for ISO PTDs 31 to 0.
0 — No OR condition defined between ISO PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to
define a certain OR condition.
Table
58) corresponds to one of the 32 INT PTDs defined,
Table 57
Table 59
Hi-Speed USB OTG controller
for bit description. For details,
for bit description. For details,
Section
© NXP B.V. 2007. All rights reserved.
ISP1761
7.4.
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