ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 58

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
Table 59.
Table 60.
Table 61.
Table 62.
ISP1761_4
Product data sheet
Bit
31 to 0
Bit
31 to 0
Bit
31 to 0
Bit
31 to 0 ATL_IRQ_MASK_
Symbol
AND[31:0]
Symbol
INT_IRQ_MASK_
AND[31:0]
Symbol
ATL_IRQ_MASK_
OR[31:0]
Symbol
ISO_IRQ_MASK_
AND[31:0]
ATL IRQ Mask OR register (address 0320h) bit description
ISO IRQ Mask AND register (address 0324h) bit description
INT IRQ MASK AND register (address 0328h) bit description
ATL IRQ MASK AND register (address 032Ch) bit description
8.4.6 ISO IRQ MASK AND register
8.4.7 INT IRQ MASK AND register
8.4.8 ATL IRQ MASK AND register
8.5 Philips Transfer Descriptor (PTD)
Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a
hardware IRQ mask for each PTD done map. For details, see
Table 60
Each bit of this register (see
and is a hardware IRQ mask for each PTD done map. For details, see
Each bit of this register corresponds to one of the 32 ATL PTDs defined, and is a
hardware IRQ mask for each PTD done map. For details, see
Table 62
The standard EHCI data structures as described in
Interface Specification for Universal Serial Bus Rev. 1.0”
operation that is managed by the hardware state machine.
Acces
s
R/W
Access
R/W
Access Value
R/W
Access Value
R/W
provides the bit description of the register.
shows the bit description of the register.
Value
0000 0000h ATL IRQ Mask AND: Represents a direct map for ATL PTDs 31 to 0.
0000 0000h
0000 0000h ISO IRQ Mask AND: Represents a direct map for ISO PTDs 31 to 0.
Value
0000 0000h
Rev. 04 — 5 March 2007
Description
0 — No OR condition defined between ATL PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to define
a certain AND condition between the 32 ATL PTDs.
Description
0 — No AND condition defined between ISO PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to
define a certain AND condition between the 32 INT PTDs.
Description
INT IRQ Mask AND: Represents a direct map for INT PTDs 31 to 0.
0 — No OR condition defined between INT PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to
define a certain AND condition between the 32 INT PTDs.
Description
ATL IRQ Mask OR: Represents a direct map for ATL PTDs 31 to 0.
0 — No OR condition defined between ATL PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to
define a certain OR condition.
Table
61) corresponds to one of the 32 INT PTDs defined,
Ref. 2 “Enhanced Host Controller
are optimized for the bus master
Hi-Speed USB OTG controller
Section
Section
7.4.
7.4.
Section
© NXP B.V. 2007. All rights reserved.
ISP1761
7.4.
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