ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 59

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ISP1761ET

Manufacturer Part Number
ISP1761ET
Description
USB Interface IC USB 2.0 HS OTG HOST
Manufacturer
NXP Semiconductors
Datasheet

Specifications of ISP1761ET

Operating Supply Voltage
1.65 V to 3.6 V
Lead Free Status / Rohs Status
 Details
Other names
ISP1761ET,557

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NXP Semiconductors
ISP1761_4
Product data sheet
The PTD structures of the ISP1761 are translations of EHCI data structures that are
optimized for the ISP1761. It, however, still follows the basic EHCI architecture. This
optimized form of EHCI data structures is necessary because the ISP1761 is a slave Host
Controller and has no bus master capability.
EHCI manages schedules in two lists: periodic and asynchronous. Data structures are
designed to provide the maximum flexibility required by USB, minimize memory traffic,
and reduce hardware and software complexity. The ISP1761 controller executes
transactions for devices by using a simple shared-memory schedule. This schedule
consists of data structures organized into three lists.
qISO — Isochronous transfer
qINTL — Interrupt transfer
qATL — Asynchronous transfer; for the control and bulk transfers
The system software maintains two lists for the Host Controller: periodic and
asynchronous.
The ISP1761 has a maximum of 32 ISO, 32 INTL and 32 ATL PTDs. These PTDs are
used as channels to transfer data from the shared memory to the USB bus. These
channels are allocated and de-allocated on receiving the transfer from the core USB
driver.
Multiple transfers are scheduled to the shared memory for various endpoints by traversing
the next link pointer provided by endpoint data structures, until it reaches the end of the
endpoint list. There are three endpoint lists: one for ISO endpoints, and the other for INTL
and ATL endpoints. If the schedule is enabled, the Host Controller executes the ISO
schedule, followed by the INTL schedule, and then the ATL schedule.
These lists are traversed and scheduled by the software according to the EHCI traversal
rule. The Host Controller executes scheduled ISO, INTL and ATL PTDs. The completion of
a transfer is indicated to the software by the interrupt that can be grouped under various
PTDs by using the AND or OR registers that are available for each schedule type: ISO,
INTL and ATL. These registers are simple logic registers to decide the completion status
of group and individual PTDs. When the logical conditions of the Done bit is true in the
shared memory, it means that PTD has completed.
There are four types of interrupts in the ISP1761: ISO, INTL, ATL and SOF. The latency
can be programmed in multiples of SOF (125 s).
The NextPTD pointer is a feature that allows the ISP1761 to jump unused and skip PTDs.
This will improve the PTD transversal latency time. The NextPTD pointer is not meant for
same or single endpoint. The NextPTD works only in forward direction.
The NextPTD traversal rules defined by the ISP1761 hardware are:
1. Start the PTD memory vertical traversal, considering the skip and LastPTD
2. If the current PTD is active and not done, perform the transaction.
3. Follow the NextPTD pointer as specified in bits 4 to 0 of DW4.
4. If combined with LastPTD, the LastPTD setting must be at a higher address than the
information, as follows.
NextPTD specified. So both are set in a logical manner.
Rev. 04 — 5 March 2007
Hi-Speed USB OTG controller
© NXP B.V. 2007. All rights reserved.
ISP1761
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