ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 63

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
Table 64.
ISP1761_4
Product data sheet
Bit
56 to 55
54 to 51
50 to 47
46 to 32
DW2
31 to 29
28 to 25
24
23 to 8
7 to 0
DW1
63 to 47
46
45 to 44
43 to 42
41 to 35
34 to 32
DW0
31
High-speed bulk IN and OUT: bit description
Symbol
Cerr[1:0]
NakCnt[3:0]
reserved
NrBytes
Transferred
[14:0]
reserved
RL[3:0]
reserved
DataStart
Address[15:0]
reserved
reserved
S
EPType[1:0]
Token[1:0]
DeviceAddress
[6:0]
EndPt[3:1]
EndPt[0]
Access
HW — writes
SW — writes
HW — writes
SW — writes
-
HW — writes
SW — writes
0000
-
SW — writes -
-
SW — writes -
-
-
SW — writes -
SW — writes -
SW — writes -
SW — writes -
SW — writes -
SW — writes -
Value
-
-
-
-
-
-
-
-
Rev. 04 — 5 March 2007
Description
Error Counter: This field corresponds to the Cerr[1:0] field in TD.
The default value of this field is zero for isochronous transactions.
00 — The transaction will not retry.
11 — The transaction will retry three times. Hardware will
decrement these values.
NAK Counter: This field corresponds to the NakCnt field in TD.
Software writes for the initial PTD launch. The V bit is reset if
NakCnt decrements to zero and RL is a non-zero value. It reloads
from RL if transaction is ACK-ed.
-
Number of Bytes Transferred: This field indicates the number of
bytes sent or received for this transaction. If Mult[1:0] is greater
than one, it is possible to store intermediate results in this field.
Set to 0 for asynchronous TD.
Reload: If RL is set to 0h, hardware ignores the NakCnt value. RL
and NakCnt are set to the same value before a transaction.
Always 0 for asynchronous TD.
Data Start Address: This is the start address for data that will be
sent or received on or from the USB bus. This is the internal
memory address and not the direct CPU address.
RAM address = (CPU address
-
Always 0 for asynchronous TD.
This bit indicates whether a split transaction has to be executed:
0 — High-speed transaction
1 — Split transaction
Transaction type:
00 — Control
10 — Bulk
Token: Identifies the token Packet Identifier (PID) for this
transaction:
00 — OUT
01 — IN
10 — SETUP
11 — PING (written by hardware only).
Device Address: This is the USB address of the function
containing the endpoint that is referred to by this buffer.
Endpoint: This is the USB address of the endpoint within the
function.
Endpoint: This is the USB address of the endpoint within the
function.
…continued
Hi-Speed USB OTG controller
400h) / 8
© NXP B.V. 2007. All rights reserved.
ISP1761
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