ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 99

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
10. Peripheral Controller
ISP1761_4
Product data sheet
10.1.1.1 DMA for the IN endpoint
10.1.1.2 DMA for the OUT endpoint
10.1.1.3 DMA initialization
10.1.1 Direct Memory Access (DMA)
10.1 Introduction
The design of the Peripheral Controller in the ISP1761 is compatible with the NXP
ISP1582 Hi-Speed Universal Serial Bus peripheral controller IC. The functionality of the
Peripheral Controller in the ISP1761 is similar to the ISP1582 in 16-bit bus mode. In
addition, the register sets are also similar, with only a few variations.
The USB Chapter 9 protocol handling and data transfer operations of the Peripheral
Controller are executed using external firmware. The external microcontroller or
microprocessor can access the Peripheral Controller-specific registers through the local
bus interface. The transfer of data between a microprocessor and the Peripheral
Controller can be done in PIO mode or programmed DMA mode.
For details on general functional description of the Peripheral Controller, refer to the
ISP1582 data sheet. For details on the software programming, refer to
Firmware Programming Guide (AN10039)”
(AN10031)”.
The DMA controller of the ISP1761 is used to transfer data between the system memory
and endpoints buffers. It is a slave DMA controller that requires an external DMA master
to control the transfer.
When the internal DMA is enabled and at least one buffer is free, the DC_DREQ line is
asserted. The external DMA controller then starts negotiating for control of the bus. As
soon as it has access, it asserts the DC_DACK line and starts writing data. The burst
length is programmable. When the number of bytes equal to the burst length has been
written, the DC_DREQ line is de-asserted. As a result, the DMA controller de-asserts the
DC_DACK line and releases the bus. At that moment, the whole cycle restarts for the next
burst. When the buffer is full, the DC_DREQ line is de-asserted and the buffer is validated,
which means that it is sent to the host at the next IN token. When the DMA transfer is
terminated, the buffer is also validated, even if it is not full.
When the internal DMA is enabled and at least one buffer is full, the DC_DREQ line is
asserted. The external DMA controller then starts negotiating for control of the bus. As
soon as it has access, it asserts the DC_DACK line and starts reading data. The burst
length is programmable. When the number of bytes equal to the burst length has been
read, the DC_DREQ line is de-asserted. As a result, the DMA controller de-asserts the
DC_DACK line and releases the bus. At that moment, the whole cycle restarts for the next
burst. When all the data is read, the DC_DREQ line is de-asserted and the buffer is
cleared. This means that it can be overwritten when a new packet arrives.
To reduce the power consumption, a controllable clock that drives DMA controller circuits
is turned off, by default. If the DMA functionality is required by an application, DMACLKON
(bit 9) of the Mode register (address: 020Ch) must be enabled during initialization of the
Rev. 04 — 5 March 2007
and
Ref. 4 “ISP1582/83 Control Pipe
Hi-Speed USB OTG controller
Ref. 6 “ISP1582/83
© NXP B.V. 2007. All rights reserved.
ISP1761
99 of 163