FM18L08-70-S Ramtron, FM18L08-70-S Datasheet

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... FM18L08-70- access, 32-pin “Green” TSOP FM18L08-70 access, 28-pin SOIC FM18L08-70 access, 28-pin DIP FM18L08-70- access, 28-pin “Green” SOIC FM18L08-70- access, 28-pin “Green” DIP * End of life. Last time buy Nov. 2009. Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 http://www ...

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... Address changes that occur after /CE goes low will be ignored until the next falling edge occurs. /OE Input Output Enable: Asserting /OE low causes the FM18L08 to drive the data bus when valid data is available. Deasserting /OE high causes the DQ pins to be tri-stated. /WE Input Write Enable: Asserting /WE low causes the FM18L08 to write the contents of the data bus to the address location latched by the falling edge of /CE ...

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... All data written to the part is immediately nonvolatile with no delay. Functional operation of the FRAM memory is the same as SRAM type devices, except the FM18L08 requires a falling edge of /CE to start each memory cycle. Memory Operation Users access 32,768 memory locations each with 8 data bits through a parallel interface ...

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... Figure 2 below. Also shown is a common SRAM signal relationship that will not work for the FM18L08. The reason for /CE to strobe for each address is two- fold: it latches the new address and creates the necessary precharge period while /CE is high. ...

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... MCU/MPU pin tri-states during the reset condition. The pullup resistor value should be chosen to ensure the /CE pin tracks V a high enough value that the current drawn when /CE is low is not an issue. level. DD MCU/ MPU Figure 3. Use of Pullup Resistor on /CE DD FM18L08 yet FM18L08 A(14: ...

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... Sept. 2009 Description SS SS (JEDEC Std JESD22-A114-B) (JEDEC Std JESD22-A115-A) = 3.0V to 3.65V) DD Min Typ 3 2.0 -0.5 2.4 = -1.0 mA 3.2 mA) FM18L08 Ratings -1.0V to +5.0V -1.0V to +5.0V and V IN < V + +125 C 300 C 4kV 400V MSL-1 (SOIC/DIP) MSL-2 (TSOP) Max Units Notes 3. 400 ...

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... I/O C Input Capacitance IN Rev. 3.5 Sept. 2009 = 3.0V to 3.65V) DD Min 70 140 3.0V to 3.65V) DD Min 70 70 140 Min Units 45 Years = 3.0V to 3.65V) DD Min Units 1 S (min 3.3V) DD Max Units FM18L08 Max Units Notes 70 ns 2,000 Max Units Notes 2,000 Notes 1 Notes Notes ...

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... AC Test Conditions Input Pulse Levels Input rise and fall times Input and output timing levels Read Cycle Timing CE A0-14 OE DQ0-7 Write Cycle Timing - /CE Controlled Timing CE A0- DQ0-7 Rev. 3.5 Sept. 2009 Equivalent AC Load Circuit 0 0 1.5V Output FM18L08 1.3V 3300 OHZ ...

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... Write Cycle Timing - /WE Controlled Timing CE A0- DQ0-7 out DQ0-7 in Power Cycle Timing VDD CE Rev. 3.5 Sept. 2009 VDD min FM18L08 VDD min ...

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... XXXX= part number, S=speed (-70), P= package type (-SG) R=rev code, YY=year, WW=work week, LLLLLL= lot code B rev., Year 2006, Work Week 30, Lot code 50013G RAMTRON FM18L08-70-SG B063050013G FM18L08 0.25 0.75 0. 0.10 0.40 1 ...

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... BSC 0.005 min. DIP Package Marking Scheme Legend: RAMTRON XXXXXXX-S-P RYYWWLLLLLLL Example: FM18L08, 70ns speed, “Green” DIP package, Rev. 3.5 Sept. 2009 1.380 1.565 0.014 0.022 XXXX= part number, S=speed (-70), P= package type (-PG) R=rev code, YY=year, WW=work week, LLLLLL= lot code B rev ...

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... TSOP Package Marking Scheme Legend: XXXXXX= part number, SP= speed/package (-70TG) R=rev code, YY=year, WW=work week, LLLLLL= lot code RAMTRON XXXXXXX-SP YYWWLLLLLL Example: FM18L08-70-TG, “green” TSOP package, RAMTRON FM18L08-70TG B065160012T2 Rev. 3.5 Sept. 2009 B rev., Year 2006, Work Week 51, Lot 60012T2 ...

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... Added recommendation on CE pin during power cycles. Added TSOP packaging option. Updated TSOP MSL rating. Redraw package outlines, added marking scheme to SOIC/DIP. Extended data retention to 45 years based on recent test results. Not Recommended for New Designs. Last time buy Nov. 2009 alternative, use the FM28V020 device. FM18L08 ...