58T1895

H5PS1G83EFR-S6C

Manufacturer Part NumberH5PS1G83EFR-S6C
Description58T1895
ManufacturerHYNIX SEMICONDUCTOR
H5PS1G83EFR-S6C datasheet
 

Specifications of H5PS1G83EFR-S6C

Memory TypeSDRAMMemory Configuration128M X 8
Access Time15nsMemory Case StyleFBGA
No. Of Pins60Operating Temperature Range0°C To +85°C
Memory Size1 GbitRohs CompliantYes
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1Gb DDR2 SDRAM
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.4 / Nov 2008
H5PS1G43EFR
H5PS1G83EFR
H5PS1G63EFR
H5PS1G43EFR
H5PS1G83EFR
H5PS1G63EFR
1

H5PS1G83EFR-S6C Summary of contents

  • Page 1

    ... DDR2 SDRAM This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4 / Nov 2008 H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR 1 ...

  • Page 2

    ... Revision Details Rev. 0.1 Initial data sheet released 0.2 IDD data Updated 0.3 Editorial Correction (added S6) 0.4 Editorial change on T Rev. 0.4 / Nov 2008 History OPER H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR Draft Date May. 2008 Aug. 2008 Sep. 2008 Nov. 2008 2 ...

  • Page 3

    ... Differential AC Output Parameters 3.3 Output Buffer Levels 3.3.1 Output AC Test Conditions 3.3.2 Output DC Current Drive 3.3.3 OCD default characteristics 3.4 IDD Specifications & Measurement Conditions 3.5 Input/Output Capacitance 4. AC Timing Specifications 5. Package Dimensions Rev. 0.4 / Nov 2008 H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR 3 ...

  • Page 4

    ... Operating Frequency table for complete part number. Hynix lead & halogen-free products are compliant to RoHS. Rev. 0.4 / Nov 2008 Operating Frequency Grade tCK(ns Ball C4 3. Ball S6 2.5 S5 2.5 H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR CL tRCD tRP Unit Clk Clk Clk Clk ...

  • Page 5

    ... Rev. 0.4 / Nov 2008 (Top view: see balls through package VSS VDDQ C DQ3 D E VSS BA1 ITEMS # of Bank Page size H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR VSSQ DQS VDDQ DQS VSSQ NC VDDQ DQ0 VDDQ DQ2 VSSQ NC VSSDL CK VDD RAS CK ODT CAS VDD A6 A4 A11 A8 VSS ...

  • Page 6

    ... VSS A DM/RDQS B VDDQ C DQ3 D E VSS BA1 ITEMS # of Bank BA0, BA1, BA2 Page size H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR VSSQ DQS VDDQ DQS VSSQ DQ7 VDDQ DQ0 VDDQ DQ2 VSSQ DQ5 VSSDL CK VDD RAS CK ODT CAS VDD A6 A4 A11 A8 ...

  • Page 7

    ... NC F LDM G VDDQ DQ1 H DQ3 J VSS VREF WE K CKE L BA1 BA0 NC, A14 A12 R H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR VSSQ UDQS VDDQ UDQS VSSQ DQ15 VDDQ DQ8 VDDQ DQ10 VSSQ DQ13 VSSQ LDQS VDDQ LDQS VSSQ DQ7 VDDQ DQ0 VDDQ DQ2 VSSQ DQ5 VSSDL ...

  • Page 8

    ... LDQS/LDQS and UDQS/UDQS "single-ended DQS signals" refers to any of the following with A10 = 1 of EMR(1) x4 DQS x8 DQS x8 DQS, RDQS, x16 LDQS and UDQS H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR DESCRIPTION has become stable during the power on and initialization if EMR(1)[A11 EMR(1)[A11 EMR(1)[A11 EMR(1)[A11 ...

  • Page 9

    ... Supply SSDL VDD Supply V Supply SS V Supply REF Rev. 0.4 / Nov 2008 No Connect: No internal electrical connection is present. DQ Power Supply: 1.8V +/- 0.1V DQ Ground DLL Power Supply: 1.8V +/- 0.1V DLL Ground Power Supply: 1.8V +/- 0.1V Ground Reference voltage. H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR -Continued- DESCRIPTION 9 ...

  • Page 10

    ... JESD51-2 standard 85~95° Double refresh rate(tREFI: 3.9us) is required, and to enter the self refresh mode at this tem- OPER perature range it must be required an EMRS command to change itself refresh rate. Rev. 0.4 / Nov 2008 H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR Rating Units - ...

  • Page 11

    ... V (ac) to test pin separately, then measure current I (ac), and VDDQ values defined in SSTL_18 IL V (ac (ac Rtt(eff) = I(V (ac delta 100% VDDQ H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR Units Max. 1.9 V 1.9 V 1.9 V 0.51*VDDQ mV VREF+0.04 V MIN NOM MAX UNITS NOTES ohm 120 150 ...

  • Page 12

    ... DDR2 400,533 Min. Max. Min. - VREF + 0.200 - VREF - 0.250 Condition to V max for falling edges as shown in the figure below. IL(ac) delta TR max IL(ac) Rising Slew = H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR Max. Units VDDQ + 0.3 V VREF - 0.125 V DDR2 667,800 Units Max VREF - 0.200 V Value Units 0 ...

  • Page 13

    ... VDDQ. VOX(AC) indicates the voltage at which differential output signals must cross. Rev. 0.4 / Nov 2008 Min. 0.5 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V DDQ SSQ < Differential signal levels > Min. 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR Max. Units Notes VDDQ + 0 Crossing point Max. Units Notes V ...

  • Page 14

    ... V OUT DDQ OH /I must be less than 21 ohm for values of V OUT OL TT are based on the conditions given in Notes 1 and 2. They are used to test min plus a noise margin and V IH H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR SSTL_18 Class II Units 0 DDQ SSTl_18 Units - 13.4 mA 13.4 mA ...

  • Page 15

    ... Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification. Rev. 0.4 / Nov 2008 Parameter Min - 0 0 Sout 1.5 VTT 25 ohms Reference point H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR Nom Max Unit Notes - - ohms 1 1.5 ohms 6 4 ohms ...

  • Page 16

    ... H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR DDR2 667 DDR2 800 x16 x4/x8 x16 115 85 120 200 170 230 185 160 215 165 170 170 260 230 290 Units ...

  • Page 17

    ... RCD = 1* t CK(IDD); CKE is HIGH HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions Rev. 0.4 / Nov 2008 Conditions Fast PDN Exit MR(12 Slow PDN Exit MR(12 H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR Units ...

  • Page 18

    ... SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes. Rev. 0.4 / Nov 2008 H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR 18 ...

  • Page 19

    ... DDR2- 667 5-5-5 6-6-6 5 7.5 7.5 7 2.5 2 70000 70000 70000 12 105 105 105 127.5 127.5 127.5 197.5 197.5 197.5 H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR DDR2- DDR2- 533 400 4-4-4 3-3-3 Units 4 3 tCK 7 70000 70000 105 105 ns 127.5 127.5 ns 197 ...

  • Page 20

    ... Max Min CCK 1.0 2.0 1.0 CDCK x 0. 1.0 2.0 1.0 CDI x 0.25 x CIO 2.5 4.0 2.5 CDIO x 0.5 x H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR DDR2 800 Units Max Min Max 2.0 1.0 2.0 pF 0.25 x 0.25 pF 2.0 1.0 1.75 pF 0.25 x 0.25 pF 3.5 2.5 3.5 pF ...

  • Page 21

    ... T CASE 3.9 ℃ DDR2-667 min min min 6-6-6 4-4-4 5-5 H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR 2Gb 4Gb Units Notes 105 127.5 195 327.5 ns 7.8 7.8 7.8 7.8 us 3.9 3.9 3.9 3.9 us DDR2-533 DDR2-400 Units Notes min min 4-4-4 3-3 tCK 15 ...

  • Page 22

    ... H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR DDR2-533 Unit Note min max -500 +500 ps -450 +450 ps 0.45 0.55 tCK 0.45 0.55 tCK min(tCL 11,12 tCH) 3750 8000 ...

  • Page 23

    ... C(max)+1 tANPD 3 tAXPD 8 tOIT 0 12 tIS+tCK+tI tDelay H H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR -Continued- DDR2-533 Units Notes min max 37 tCK WR+tRP* - tCK 7 7.5 ns tRFC + 10 ns 200 - tCK 2 ...

  • Page 24

    ... WR+tnRP - H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR (DDR2-667 and DDR2-800) DDR2-800 Unit min max -400 +400 ps -350 +350 ps 0.48 0.52 tCK(avg) 0.48 0.52 tCK(avg) min(tCL(abs tCH(abs)) 2500 8000 ...

  • Page 25

    ... H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR -Continued- DDR2-800 Unit Notes min max 7 24,32 7.5 ns 3,32 tRFC + 10 ns 200 - nCK 2 - nCK 2 nCK ...

  • Page 26

    ... Output slew rate is characterized under the test conditions as shown below. VDDQ DUT Rev. 0.4 / Nov 2008 DQ DQS Output DQS RDQS Timing 25 RDQS reference point AC Timing Reference Load DQ Output DQS, DQS RDQS, RDQS 25 Test point Slew Rate Test Load H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR DDQ Ω DDQ Ω 26 ...

  • Page 27

    ... Rev. 0.4 / Nov 2008 t t DQSH DQSL DQS DQS t WPRE V (ac (ac (ac) IH DMin DMin V (ac) IL Figure -- Data input (write) timing RPRE Q t DQSQmax t QH Figure -- Data output (read) timing H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR t WPST V (dc (dc (dc) IH DMin DMin V (dc RPST DQSQmax ...

  • Page 28

    ... V/ns △ △ △ △ △ △ tDS tDH tDS tDH tDS 45 100 - -13 - - H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR 1.4 V/ns 1.2 V/ns 1.0 V/ns △ △ △ △ △ △ tDH tDS tDH tDS tDH tDS - - - - - - - - - - - - - -59 -31 -47 -19 - -74 -89 -62 -77 -50 - ...

  • Page 29

    ... H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR 1.4 V/ns 1.2 V/ns 1.0 V/ns △ △ △ △ △ △ tDH tDS tDH tDS tDH tDS - - - - - - - - - - - - - -27 -29 - -44 -43 -62 -60 -86 - -67 -61 -85 -78 -109 -108 -152 -96 -85 -114 -102 -138 -132 -181 -183 -248 ...

  • Page 30

    ... REF V (dc)max IL V (ac)max IL Vss Delta TF Setup Slew Rate V = Falling Signal Rev. 0.4 / Nov 2008 nominal slew rate Delta TR (dc)-V (ac)max Setup Slew Rate REF IL Rising Signal Delta TF H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR nominal slew rate REF region V (ac)min-V (dc) REF IH = Delta TR 30 ...

  • Page 31

    ... Vss Delta TF Setup Slew Rate Tangent line[V = Falling Signal Rev. 0.4 / Nov 2008 nominal line Tangent line Delta TR Setup Slew Rate Tangent line[V = Rising Signal (dc)-V (ac)max] REF IL Delta TF H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR tangent line REF region (ac)min-V (dc)] REF IH Delta TR 31 ...

  • Page 32

    ... REF V (dc)max IL V (ac)max IL Vss V Hold Slew Rate = Rising Signal Rev. 0.4 / Nov 2008 REF nominal slew rate Delta TR (dc)-V (dc)max Hold Slew Rate REF IL Falling Signal Delta TR H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR nominal slew rate Delta TF V (dc)min - V (dc) IH REF = Delta TF 32 ...

  • Page 33

    ... IL Vss Hold Slew Rate Tangent line[V = Rising Signal Rev. 0.4 / Nov 2008 Tangent nominal line line Delta TR (dc)-V (ac)max] REF IL Delta TR Hold Slew Rate = Falling Signal H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR nominal line tangent line Delta TF Tangent line[V (ac)min-V (dc)] REF IH Delta TF 33 ...

  • Page 34

    ... H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR 1.0 V/ns △ tIH Uni ts Note s +154 ps 1 +149 ps 1 +143 ps 1 +135 ps 1 +105 ps 1 +81 ps ...

  • Page 35

    ... Hold(tIH) nominal slew rate for a falling signal is defined as the REF (dc). If the actual signal is always later than the nominal slew rate REF (dc) region’, use nominal slew rate for derating value(see Fig.c) If the actual H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR 1.0 V/ns △ tIS △ tIH Uni ts ...

  • Page 36

    ... Below figure shows a method to calculate the point when device is no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measure- ment points are not critical as long as the calculation is consistent. Rev. 0.4 / Nov 2008 H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR 36 ...

  • Page 37

    ... VOL + 1xmV VTT -xmV VOL + 2xmV VTT - 2xmV tLZ , tRPRE begin point = 2*T1-T2 (ac) level to the differential data strobe crosspoint for a falling signal IL Differential Input waveform timing tDS tDH tDS tDH H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR tLZ tRPRE begin point DDQ V min IH(ac) V min ...

  • Page 38

    ... For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU {tPARAM / tCK (avg)}, which is in clock cycles, assuming all input clock jitter specifications Rev. 0.4 / Nov 2008 H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR (ac) level for a rising sig- IH (dc) level for a rising sig- ...

  • Page 39

    ... H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR DDR2-800 Units Notes min max -100 100 -200 200 ps 35 -160 160 ps 35 -150 ...

  • Page 40

    ... H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR max Units tCK (avg), max + tJIT (per), max ps tCH (avg), max * tCK (avg), max ps ...

  • Page 41

    ... HIGH pulse width of 0.5 relative to tCK (avg). tAOF, min and tAOF, max should each be derated by the same amount as the actual amount of tCH (avg) offset present at the DRAM input with respect to 0.5. For example input clock has a worst case tCH (avg) of 0.48, the tAOF, min should be derated by sub- Rev. 0.4 / Nov 2008 H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR 41 ...

  • Page 42

    ... Thus the final derated values for tAOF are; tAOF, min (derated _ final) = tAOF, min (derated tJIT (duty), max - tERR(6-10per),max} tAOF, max (derated _ final) = tAOF, max (derated tJIT (duty), min - tERR(6-10per),min} Rev. 0.4 / Nov 2008 H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR 42 ...

  • Page 43

    ... A1 BALL MARK < Top View> 60X Φ0.45 ± 0.05 < Bottom View> Rev. 0.4 / Nov 2008 2.10 ± 0.10 A1 BALL MARK 1.60 1.60 0.80 Note: All dimensions are in millimeters. H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR 2-R0.13MAX < SIDE View> 1.10 ± 0.10 0.34 ± 0.05 43 ...

  • Page 44

    ... Top View> 84X Φ0.45 ± 0.05 < Bottom View> Rev. 0.4 / Nov 2008 8.00 ± 0.10 0. 6.40 2.10 ± 0.10 A1 BALL MARK 0.80 1.60 1.60 H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR 2-R0.13MAX < SIDE View> 1.10 ± 0.10 0.34 ± 0.05 Note: All dimensions are in millimeters. 44 ...