H5TQ2G63BFR-H9C HYNIX SEMICONDUCTOR, H5TQ2G63BFR-H9C Datasheet
H5TQ2G63BFR-H9C
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H5TQ2G63BFR-H9C Summary of contents
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... Contents are subject to change at any time without notice. Rev. 0.5 / Aug. 2010 This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. (RoHS Compliant) H5TQ2G63BFR H5TQ2G63BFR 1 ...
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... Changed & Updated Idd Specification table Changed Speed Bin for 800/900MHz/1.0Ghz Changed Electrical Characteristics and AC Timing 0.5 Changed Speed Bin for 800/900MHz Rev. 0.5 / Aug. 2010 History Preliminary Initial Release @800/900Mhz, 1.0Ghz H5TQ2G63BFR Page Draft Date Remark Sep. 2009 Preliminary Oct. 2009 65 Nov.2009 ...
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... Auto SElf-Refresh(ASR) and Self-Refresh Temperature(SRT) 1.8.4 Dynamic ODT(Rtt_WR) 1.9 Mode Register(MR3) 1.10 Multi-Purposer Register(MPR) 1.10.1 Multi Purpose Register 1.10.2 MPR Functional Description 1.10.3 MPR Register Address Definition 1.10.4 Relevant Timing Parameters 1.10.5 Protocol Example Rev. 0.5 / Aug. 2010 Table of Contents H5TQ2G63BFR 3 ...
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Command Description 2.1 Command Truth Table 2.2 Clock Enable (CKE) Truth Table for Synchronous Transitions 3. Absolute Maximum Ratings 4. Operating Conditions 4.1 Operating Temperature Condition 4.2 DC Operating Conditions 5. AC and DC Input Measurement Levels 5.1 AC ...
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... ODT Timing Reference Load 8. IDD Specification Parameters and Test Conditions 8.1 IDD Measurement Conditions 8.2 IDD Specifications 8.2.1 IDD6 Current Definition 8.2.2 IDD6TC Specification (see notes 1~2) 9. Input/Output Capacitance 10. Standard Speed Bins 11. Electrical Characteristics and AC Timing 12. Package Dimensions Rev. 0.5 / Aug. 2010 H5TQ2G63BFR 5 ...
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... DESCRIPTION The H5TQ2G63BFR is a 2,147,483,648-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. Hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sam- pled on both rising and falling edges of it ...
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... BA0 BA2 A13 (Top View: See the balls through the Package) Populated ball Ball not populated Back View Populated ball Ball not populated H5TQ2G63BFR DQU4 VDDQ VSS DQSU DQU6 VSSQ DQSU DQU2 VDDQ DQU0 VSSQ VDD DML VSSQ VDDQ DQL1 DQL3 ...
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... Note1: Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered. Page size is per bank, calculated as follows: COLBITS page size = 2 * ORG ÷ 8 where COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits Rev. 0.5 / Aug. 2010 128Mb BA0 - BA2 A10/AP A12/ A13 H5TQ2G63BFR 8 ...
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... Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH. RESET must be HIGH during normal operation. RESET Input RESET is a CMOS rail to rail signal with DC high and low at 80% and 20 for DC high and 0.30V for DC low. Rev. 0.5 / Aug. 2010 H5TQ2G63BFR Function , i.e. 1.20V DD 9 ...
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... Power Supply: 1.5 V +/- 0.075 Supply Ground SS V Supply Reference voltage for DQ REFDQ Supply Reference voltage V REFCA Reference Pin for ZQ calibration ZQ Supply Note: Input only pins (BA0-BA2, A0-A15, RAS, CAS, WE, CS, CKE, ODT, DM, and RESET) do not supply termination. Rev. 0.5 / Aug. 2010 H5TQ2G63BFR Function 10 ...
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... VALID MRS /DES /DES VALID VALID VALID VALID VALID Updating Settings tMRD ODTLoff+1 VALID VALID VALID VALID VALID Figure 4. tMRD Timing H5TQ2G63BFR Tb1 Tb2 Tc0 Tc1 NOP NOP MRS VALID VALID /DES /DES VALID VALID VALID VALID New Settings tMOD VALID ...
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... MRS /DES /DES /DES VALID VALID VALID VALID VALID Updating Settings tMOD ODTLoff+1 VALID VALID VALID VALID VALID Figure 5. tMOD Timing H5TQ2G63BFR Ta3 Ta4 Tb0 Tb1 Tb2 NOP NOP VALID VALID /DES /DES VALID VALID VALID VALID New Settings VALID VALID ...
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... The table only shows the encodings for Write Recovery. For actual Write recovery timing, please refer to AC timing table. Figure 6. DDR3 SDRAM mode register set (MR0) Rev. 0.5 / Aug. 2010 DLL TM CAS Latency A7 mode 0 Normal 1 Test Write recovery for autoprecharge A11 A10 A9 WR(cycles H5TQ2G63BFR Address Field Mode Register 0 RBT Read Burst Type 0 Sequential Interleave ...
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... 0,1,2,3,T,T,T,T 1,2,3,0,T,T,T,T 2,3,0,1,T,T,T,T 3,0,1,2,T,T,T,T 4,5,6,7,T,T,T,T 5,6,7,4,T,T,T,T 6,7,4,5,T,T,T,T 7,4,5,6,T,T,T,T 0,1,2,3,X,X,X,X 4,5,6,7,X,X,X,X 0,1,2,3,4,5,6,7 1,2,3,0,5,6,7,4 2,3,0,1,6,7,4,5 3,0,1,2,7,4,5,6 4,5,6,7,0,1,2,3 5,6,7,4,1,2,3,0 6,7,4,5,2,3,0,1 7,4,5,6,3,0,1,2 0,1,2,3,4,5,6,7 H5TQ2G63BFR burst type = Interleaved (decimal) Notes 0,1,2,3,T,T,T,T 1,2,3 1,0,3,2,T,T,T,T, 1,2,3 2,3,0,1,T,T,T,T 1,2,3 3,2,1,0,T,T,T,T 1,2,3 4,5,6,7,T,T,T,T 1,2,3 5,4,7,6,T,T,T,T 1,2,3 6,7,4,5,T,T,T,T 1,2,3 7,6,5,4,T,T,T,T 1,2,3 ...
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... DLL is frozen after entering precharge power-down (for potential power savings) and upon exit requires tXPDLL to be met prior to the next valid command. When MR0 (A12 = 1), or ‘fast-exit’, the DLL is maintained after entering precharge power-down requires tXP to be met prior to the next vaild command. Rev. 0.5 / Aug. 2010 H5TQ2G63BFR 15 ...
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... Leveling Mode MR1[bit12]=0, only RTT_Nom settings of RZQ/2, RZQ4 and RZQ/6 are allowed. *4: If RTT_Nomm is used during Writes, only the val- ues RZQ/2,RZQ/4 and RZQ/6 are allowed Note: RZQ= 240Ω Figure 7. MR1 Definition H5TQ2G63BFR Address Field Mode Register 1 AL D.I.C DLL ...
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... DRAM on DIMM. It makes it difficult ofr the Controller to maintain tDQSS, tDSS and tDSH specification. Therefore, the DDR3 SDRAM supports a ‘write leveling’ feature to allow the con- troller to compensate for skew. See “Write Leveling” for mode details. Rev. 0.5 / Aug. 2010 (AL Disabled Reserved H5TQ2G63BFR 17 ...
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... DQS, DQS, etc.) are disconnected from the device removing any loading of the output drivers. This feature may be useful when measuring module power for example. For normal operation, A12 should be set to ‘0’. Rev. 0.5 / Aug. 2010 H5TQ2G63BFR 18 ...
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... Figure 8. MR2 Definition H5TQ2G63BFR PASR CWL A0 Partial Array Self Refresh (Optional) 0 Full Array 1 Half Array (BA[2:0]=000,001,010&011) 0 Quarter Array (BA[2:0]=000&001) 1 1/8th Array (BA[2:0]=000) 0 3/4 Array (BA[2:0]=010,011,100,101,110&111) 1 Half Array (BA[2:0]=100,101,110&111) 0 Quarter Array (BA[2:0]=110&111) 1 1/8th Array (BA[2:0]=111) ...
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... DDR3 SDRAM can be changed without issuing an MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT setings. In Write leveling mode, only RTT_Nom is available. For details on Dynamic ODT operation, refer to “Dynamic ODT”. Rev. 0.5 / Aug. 2010 H5TQ2G63BFR 20 ...
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... RESET function is supported during MPR enable mode. For detailed MPR operation refer to “Multi Purpose Register”. Rev. 0.5 / Aug. 2010 MPR* 3 Normal operation* Dataflow from MPR Figure 9. MR3 Definition H5TQ2G63BFR Address Field Mode Register 3 MPR MPR Loc MPR Address A1 A0 MPR location 0 0 Predefined pattern* ...
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... Table 5. MPR MR3 Register Definition Normal operation, no MPR transaction. All subsequent Reads will come from DRAM array. All subsequent Write will go to DRAM array. Enable MPR mode, subsequent RD/RDA commands defined by MR3 H5TQ2G63BFR Multi purpose register Pre-defined data for Reads Function A[1:0] ...
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... DDR3 SDRAM. • Regular read latencies and AC timings apply. • DLL must be locked prior to MPR Reads. Note: * Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent. Rev. 0.5 / Aug. 2010 H5TQ2G63BFR 23 ...
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... BC4 100b BL8 000b RFU BC4 000b BC4 100b H5TQ2G63BFR Burst Order and Data Pattern Burst order 0,1,2,3,4,5,6,7 Pre-defined Data Pattern [0,1,0,1,0,1,0,1] Burst order 0,1,2,3 Pre-defined Data Pattern [0,1,0,1] Burst order 4,5,6,7 Pre-defined Data Pattern [0,1,0,1] Burst order 0,1,2,3,4,5,6,7 Burst order 0,1,2,3 ...
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... Memory Controller must drive 0 on A[2:0]. Figure 11. MPR Readout of predefined pattern, BL8 fixed burst order, single readout Rev. 0.5 / Aug. 2010 Tc0 Tc1 Tc2 Tc3 Tc4 WRITE NOP NOP NOP NOP RL H5TQ2G63BFR Tc5 Tc6 Tc7 Tc8 Tc9 tMPRR tMOD NOP NOP MRS NOP NOP 3 ...
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... Figure 12. MPR Readout of predefined pattern, BL8 fixed burst order, back-to-back readout Rev. 0.5 / Aug. 2010 Tc1 Tc2 Tc3 Tc4 WRITE NOP NOP NOP H5TQ2G63BFR Tc5 Tc6 Tc7 Tc8 Tc9 NOP NOP NOP NOP NOP tMPRR TIME BREAK DON’T CARE Tc10 ...
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... A[2]=1 selects upper 4 nibble bits 4...7. Figure 13. MPR Readout of predefined pattern, BC4, lower nibble then upper readout Rev. 0.5 / Aug. 2010 Tc1 Tc2 Tc3 Tc4 WRITE NOP NOP NOP H5TQ2G63BFR Tc5 Tc6 Tc7 Tc8 Tc9 NOP NOP NOP MRS NOP tMPRR tMOD 3 VALID 0 00 ...
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... A[2]=1 selects upper 4 nibble bits 4...7. Figure 14. MPR Readout of predefined pattern, BC4, upper nibble then lower readout Rev. 0.5 / Aug. 2010 Tc1 Tc2 Tc3 Tc4 WRITE NOP NOP NOP H5TQ2G63BFR Tc5 Tc6 Tc7 Tc8 Tc9 NOP NOP NOP MRS NOP tMPRR tMOD 3 VALID 0 00 ...
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... Power Down Entry PDE Rev. 0.5 / Aug. 2010 CKE Previ Curre CS RAS CAS ous nt Cycle Cycle H5TQ2G63BFR A0- BA0- A13- A12- A10- WE A9, BA3 A15 BC AP A11 Code Row Address (RA RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU ...
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... The Deselect command performs the same function as No Operation command. 12. Refer to the CKE Truth Table for more detail with CKE transition. Rev. 0.5 / Aug. 2010 CKE Previ Curre CS RAS CAS ous nt Cycle Cycle H5TQ2G63BFR A0- WE BA0- A13- A12- A10- A9, BA3 A15 BC AP A11 Notes V 6,12 ...
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... DESELECT or NOP L DESELECT or NOP L DESELECT or NOP L DESELECT or NOP L DESELECT or NOP L DESELECT or NOP L DESELECT or NOP L REFRESH H5TQ2G63BFR 3 Action (N) Maintain Power-Down Power-Down Exit Maintain Self-Refresh Self-Refresh Exit Active Power-Down Entry Power-Down Entry 11,13,14,17 Power-Down Entry 11,13,14,17 Power-Down Entry 11,13,14,17 Precharge Power-Down Entry Precharge Power-Down Entry ...
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... JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than 0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. Rev. 0.5 / Aug. 2010 H5TQ2G63BFR Rating Units - 0 1.975 ...
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... Under all conditions, VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. Rev. 0.5 / Aug. 2010 Rating Rating Min. Typ. Max. 1.425 1.500 1.575 1.425 1.500 1.575 H5TQ2G63BFR Units Notes 1 and case Units Notes V ...
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... Illustration of Vref (DC) tolerance and Vref ac-noise limits Rev. 0.5 / Aug. 2010 Min Vref + 0.100 VSS Vref + 0.175 0.49 * VDD 0.49 * VDD to deviate from V by more than +/-1% VDD Ref Ref(DC) V ac-noise Ref H5TQ2G63BFR Max Unit Notes VDD V Vref - 0.100 Vref - 0.175 V 0.51 * VDD V 0.51 * VDD ...
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... VDD and VSS. V Cross point voltage for differential input signals (CK, DQS) Symbol Parameter Differential Input Cross Point V IX Voltage relative to VDD/2 Rev. 0.5 / Aug. 2010 Min + 0.200 Vix Definition Min - 150 H5TQ2G63BFR Max Unit Notes - 0.200 V 1 VDD CK, DQS VDD CK, DQS VSS Max ...
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... Rev. 0.5 / Aug. 2010 Measured Max Min Vref VIH (AC) min Vref VIL (AC) max VIL (DC) max Vref Vref H5TQ2G63BFR Defined by Applicable for VIH (AC) min-Vref Delta TRS Setup Vref-VIL (AC) max (tIS, tDS) Delta TFS Vref-VIL (DC) max Delta TFH VIH (DC) min-Vref (tIH, tDH) Delta TRH ...
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... The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds. Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# Rev. 0.5 / Aug. 2010 Measured Min VILdiffmax VIHdiffmin VILdiffmax Delta TFdiff H5TQ2G63BFR Defined by Max VIHdiffmin-VILdiffmax VIHdiffmin DeltaTRdiff VIHdiffmin-VILdiffmax DeltaTFdiff Delta TRdiff ...
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... Single ended output slew rate for falling edge Note: Output slew rate is verified by design and characterisation, and may not be subject to production test. Rev. 0.5 / Aug. 2010 Parameter Parameter Measured From VOL(AC) VOH(AC) H5TQ2G63BFR 800/900MHz & 1.0GHz Unit 0.8 x VDDQ V 0.5 x VDDQ V 0.2 x VDDQ V VTT + 0.1 x VDDQ V VTT - 0 ...
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... Single-ended Output Slew Rate *** For Ron = RZQ/7 setting Rev. 0.5 / Aug. 2010 Single Ended Output Slew Rate Definition Delta TFse Single Ended Output Slew Rate Definition 800/900MHz & 1.0GHz Symbol Min SRQse 2.5 H5TQ2G63BFR Delta TRse vOH(AC) V∏ vOl(AC) Max 5 Units V/ns 39 ...
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... Rev. 0.5 / Aug. 2010 Measured From VOLdiff (AC) VOHdiff (AC) VOHdiff (AC) VOLdiff (AC) Delta TFdiff Differential Output Slew Rate Definition Differential Output Slew Rate Definition 800/900MHz & 1.0GHz Symbol Min 5 H5TQ2G63BFR Defined by To VOHdiff (AC)-VOLdiff (AC) DeltaTRdiff VOHdiff (AC)-VOLdiff (AC) DeltaTFdiff Delta TRdiff vOHdiff(AC) O vOLdiff(AC) Max 10 Units ...
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... Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. CK, CK Reference Load for AC Timing and Output Slew Rate Rev. 0.5 / Aug. 2010 VDDQ 25 Ohm DQ DUT DQS DQS H5TQ2G63BFR VTT = VDDQ/2 41 ...
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... Maximum overshoot area above VDD (See Figure) Maximum undershoot area below VSS (See Figure tro fin itio n Rev. 0.5 / Aug. 2010 800MHz 0.4V 0.4V 0.33 V-ns 0.33 V- litu litu H5TQ2G63BFR Specification 900MHz 1.0GHz 0.4V 0.4V 0.4V 0.4V 0.28 V-ns 0.27 V-ns 0.28 V-ns 0.27 V- ...
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... Maximum undershoot area below VSSQ (See Figure lts ( Rev. 0.5 / Aug. 2010 800MHz 0.4V 0.4V 0.13 V-ns 0.13 V- litu litu tro rsh rsh fin itio n H5TQ2G63BFR Specification 900MHz 1.0GHz 0.4V 0.4V 0.4V 0.4V 0.11 V-ns 0.10 V-ns 0.11 V-ns 0.10 V- rsh rsh ...
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... Circuitry Like RCV, ... Output Driver: Definition of Voltages and Currents Rev. 0.5 / Aug. 2010 under the condition that RONPd is turned off under the condition that RONPu is turned off Chip in Drive Mode Output Driver Ipu RONpu RONpd Ipd H5TQ2G63BFR VDDQ DQ Iout Vout VSSQ 44 ...
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... OHdc DDQ V OMdc 0.5 × V DDQ x 100 min dTH*|Δ dVH*|ΔV| 1 dTM*|Δ dVM*|ΔV| 1 dTL*|Δ dVL*|ΔV| 1 min max 0 1.5 0 0.15 0 1.5 0 TBD H5TQ2G63BFR nom max Unit 0.6 1.0 1 0.9 1.0 1 0.9 1.0 1 0.9 1.0 1 0.9 1.0 1.1 ...
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... RTTPd) are defined as follows – DDQ Out RTT --------------------------------- = Pu I Out V Out RTT ------------ - = under the condition that RTTPu is turned off Pd I Out Rev. 0.5 / Aug. 2010 min 0 0 under the condition that RTTPd is turned off H5TQ2G63BFR max unit 1.5 %/ TBD %/ ...
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... DDQ 0.5 × V RTT 60Pd120 DDQ V OHdc 0.8 × V DDQ V OLdc 0.2 × V DDQ 0.5 × V RTT 60Pu120 DDQ V OHdc 0.8 × V DDQ RTT IL(ac) IH(ac) H5TQ2G63BFR min nom max Unit 0.6 1.00 1 0.9 1.00 1 0.9 1.00 1 0.9 1.00 1 0.9 1.00 1 ...
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... V RTT 20Pd40 DDQ V OHdc 0.8 × V DDQ V OLdc 0.2 × V DDQ 0.5 × V RTT 20Pu40 DDQ V OHdc 0.8 × V DDQ RTT IL(ac) IH(ac) w.r.t. V /2, DV DDQ M H5TQ2G63BFR min nom max Unit 0.6 1.00 1 0.9 1.00 1 0.9 1.00 1 0.9 1.00 1 0.9 1 ...
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... ODT Voltage and Temperature Sensitivity These parameters may not be subject to production test. They are verified by design and characterization Rev. 0.5 / Aug. 2010 V IH(ac) V IL(ac) – = -------------------------------------------------------- - I(VIH(ac)) I(VIL(ac)) – 100 dV*|ΔV| 1 min 0 0 H5TQ2G63BFR max dT*|Δ dV*|ΔV| RZQ/2,4,6,8, max unit 1 0.15 %/mV unit C 49 ...
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... End point: Extrapolated point at VRTT_Nom End point: Extrapolated point at VRTT_Wr and VRTT_Nom respectively RTT_Wr Setting V [V] SW1 NA 0.05 NA 0.10 NA 0.05 NA 0.10 NA 0.05 NA 0.10 NA 0. 0.20 ZQ H5TQ2G63BFR Figure Figure Figure Figure Figure Figure V [V] Note SW2 0.10 0.20 0.10 0.20 0.10 0.20 0.10 0.20 0.30 50 ...
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... DQS, DQS TDQS, TDQS Rev. 0.5 / Aug. 2010 t AON T SW2 T SW1 V SW2 V VSSQ SW1 End point: Extrapolated point at VSSQ Definition of tAON t AONPD T SW2 T SW1 V SW2 V VSSQ SW1 End point: Extrapolated point at VSSQ Definition of tAONPD H5TQ2G63BFR VTT VSSQ TD_TAON_DEF VTT VSSQ TD_TAONPD_DEF 51 ...
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... DQS, DQS TDQS, TDQS Rev. 0.5 / Aug. 2010 t AOF End point: Extrapolated point at VRTT_Nom VRTT_Nom T SW2 T SW1 V SW2 V SW1 Definition of tAOF t AOFPD End point: Extrapolated point at VRTT_Nom VRTT_Nom T SW2 T SW1 V SW2 V SW1 Definition of tAOFPD H5TQ2G63BFR VTT VSSQ TD_TAOF_DEF VTT VSSQ TD_TAOFPD_DEF 52 ...
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... DQS point at VRTT_Nom TDQS, TDQS Rev. 0.5 / Aug. 2010 Begin point: Rising edge defined by the end point of ODTLcwn4 or ODTLcwn8 t ADC T SW21 T V SW11 SW2 V SW1 VRTT_Wr Definition of tADC H5TQ2G63BFR VTT t ADC VRTT_Nom T SW22 T SW12 End point: Extrapolated point at VRTT_Wr VSSQ TD_TADC_DEF 53 ...
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... Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started. • Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW} • Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH} Rev. 0.5 / Aug. 2010 ILAC(max). IHAC(max). H5TQ2G63BFR 54 ...
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... Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported Rev. 0.5 / Aug. 2010 DDQ DDR3 SDRAM DQS, DQS DQ, DM, TDQS, TDQS V SSQ IDDQ Simulation Correction by IDDQ Measurement H5TQ2G63BFR I (optional) DDQ R 25 Ohm = TT V DDQ IDDQ Test Load IDDQ Simulation /2 55 ...
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... Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers stable at 0; Pattern Details: see Table 5 on page 44 Rev. 0.5 / Aug. 2010 800MHz 900MHz 1.25 1 128 145 Description H5TQ2G63BFR 1.0GHz Unit 1 nCK 15 nCK 52 nCK 38 nCK 15 nCK 40 nCK 6 nCK 160 nCK a) ; AL: 0; CS: High between b) ...
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... ODT Signal: stable at 0; Precharge Power Down a) ; AL: 0; CS: stable at 1; Command ODT Signal: stable at 0; Precharge Power Down a) ; AL: 0; CS: stable at 1; Command ODT Signal: stable AL: 0; CS: stable at 1; Command AL: 0; CS: stable at 1; Command ODT Signal: stable at 0 H5TQ2G63BFR b) ; ODT Signal ODT Signal: 57 ...
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... Temperature Range (SRT): Normal b) ; ODT Signal: FLOATING f) d) ;Self-Refresh Temperature Range (SRT): Extended f) d) ;Self-Refresh Temperature Range (SRT): Normal b) ; ODT Signal: FLOATING H5TQ2G63BFR a) ; AL: 0; CS: High between RD; Com AL: 0; CS: High between WR; Com AL: 0; CS: High between REF AL: 0; CS, Command AL: 0; CS, Command, b) ...
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... Sub-Loop 0, use BA[2: instead repeat Sub-Loop 0, use BA[2: instead repeat Sub-Loop 0, use BA[2: instead repeat Sub-Loop 0, use BA[2: instead repeat Sub-Loop 0, use BA[2: instead repeat Sub-Loop 0, use BA[2: instead repeat Sub-Loop 0, use BA[2: instead H5TQ2G63BFR ...
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... Sub-Loop 0, use BA[2: instead repeat Sub-Loop 0, use BA[2: instead repeat Sub-Loop 0, use BA[2: instead repeat Sub-Loop 0, use BA[2: instead repeat Sub-Loop 0, use BA[2: instead repeat Sub-Loop 0, use BA[2: instead repeat Sub-Loop 0, use BA[2: instead H5TQ2G63BFR ...
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... Sub-Loop 0, but ODT = 0 and BA[2: repeat Sub-Loop 0, but ODT = 1 and BA[2: repeat Sub-Loop 0, but ODT = 1 and BA[2: repeat Sub-Loop 0, but ODT = 0 and BA[2: repeat Sub-Loop 0, but ODT = 0 and BA[2: repeat Sub-Loop 0, but ODT = 1 and BA[2: repeat Sub-Loop 0, but ODT = 1 and BA[2: H5TQ2G63BFR ...
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... Sub-Loop 0, but BA[2: repeat Sub-Loop 0, but BA[2: repeat Sub-Loop 0, but BA[ repeat Sub-Loop 0, but BA[2: repeat Sub-Loop 0, but BA[2: repeat Sub-Loop 0, but BA[2: repeat Sub-Loop 0, but BA[2: repeat Sub-Loop 0, but BA[2: repeat Sub-Loop 0, but BA[2: repeat Sub-Loop 0, but BA[2: H5TQ2G63BFR ...
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... BA[2: repeat cycles 1...4, but BA[2: repeat cycles 1...4, but BA[2: repeat cycles 1...4, but BA[2: repeat cycles 1...4, but BA[2: repeat cycles 1...4, but BA[2: repeat cycles 1...4, but BA[2: repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary. H5TQ2G63BFR ...
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... Sub-Loop 11, but BA[2: Assert and repeat above D Command until 3* nFAW - 1, if necessary repeat Sub-Loop 10, but BA[2: repeat Sub-Loop 11, but BA[2: repeat Sub-Loop 10, but BA[2: repeat Sub-Loop 11, but BA[2: Assert and repeat above D Command until 4* nFAW - 1, if necessary H5TQ2G63BFR Data 00000000 ...
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... I 20 DD3P I 155 DD4R I 165 DD4W I 165 DD5 I 10 DD6 I 190 DD7 *IDD Values can be slightly changed when above table is updated. Rev. 0.5 / Aug. 2010 900MHz 1.0GHz Max. Max 170 185 180 200 180 200 10 12 210 230 H5TQ2G63BFR Unit Notes ...
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... TBD DDQS -0.4 0.2 TBD DI_CTRL DI_ADD_ -0.4 0.4 TBD CMD C -0.5 0.3 TBD DIO . I (CLK)) I (CLK)+C (CLK (DQS)) IO H5TQ2G63BFR 1.0GHz Max Min Max Units TBD TBD TBD pF TBD TBD TBD pF TBD TBD TBD pF TBD TBD TBD pF TBD TBD TBD pF TBD ...
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... Reserved 2.5 3.3 Reserved Reserved Reserved 1.875 2.5 Reserved Reserved Reserved 1.875 2.5 Reserved Reserved 1.5 1.875 Reserved Reserved 1.5 1.875 1.25 1.5 Reserved 1.25 1.5 5,6, 7,8, 9,10, 7,8 H5TQ2G63BFR Unit Note 1,2,3,4 1,2,3,6 ns 1,2,3,4 1,2,3,4,6 ns 1,2,3,4 1,2,3,6 ...
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... Reserved 2.5 3.3 Reserved Reserved Reserved 1.875 2.5 Reserved Reserved Reserved 1.875 2.5 Reserved Reserved 1.5 1.875 Reserved Reserved 1.5 1.875 1.25 1.5 Reserved 1.25 1.5 1.1 1.25 5,6, 7,8, 9,10, 7,8,9 H5TQ2G63BFR Unit Note 1,2,3,4 1,2,3,7 ns 1,2,3,4 1,2,3,4,7 ns 1,2,3,4 1,2,3,7 ...
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... Reserved Reserved Reserved 1.875 2.5 Reserved Reserved Reserved 1.875 2.5 Reserved Reserved 1.5 1.875 Reserved Reserved 1.5 1.875 1.25 1.5 Reserved 1.25 1.5 1.0 1.25 Reserved 1.0 1.25 5,6,7,8,9,10,11,12 5,6,7,8,9 H5TQ2G63BFR Unit Note 1,2,3,4 1,2,3,8 ns 1,2,3,4 1,2,3,4,8 ns 1,2,3,4 1,2,3,8 ns 1,2,3,4,8 ...
Page 70
... It is not a mandatory bin. Refer to supplier’s data sheet and/or the DIMM SPD information. 10. If it’s supported, the minimum tAA/tRCD/tRP that this device support is 13.125ns. Therefore, In Module application, tAA/tRCD/tRP should be programed with minimum supported values. Rev. 0.5 / Aug. 2010 = V = 1.5V +/- 0.075 V); DD H5TQ2G63BFR 70 ...
Page 71
... H5TQ2G63BFR 1.0GHz Min Max Units Notes - tCK 0.47 0.53 (avg) tCK 0.47 0.53 (avg) ps tCK - 0.43 - (avg) ...
Page 72
... Note 0.9 Note 0.3 Note 0.3 Note 0.38 - 0.38 0.38 - 0.38 0.9 - 0.9 0.3 - 0.3 -225 225 -180 180 H5TQ2G63BFR 1.0GHz Min Max Units Notes TBD TBD ps TBD TBD tCK - 0.38 - (avg) -360 180 ps - 180 tCK ...
Page 73
... K,15ns) K,15ns) 16.3 - 15.6 16.3 - 15.6 52 H5TQ2G63BFR 1.0GHz Max Min Max Units Notes 200 -360 180 ps 200 - 180 ps tCK 0.6 0.4 0.6 (avg) tCK 0.6 0.4 0.6 (avg) tCK 0.25 -0.3 0.3 (avg) ...
Page 74
... tRFC(min) tRFC(min) +10ns) +10ns) max(5nsC max(5nsC tRFC(min) tRFC(min) +10ns) +10ns) tDLLK(min tDLLK(min - ) ) tCKE(min)+1nCK tCKE(min)+1nCK H5TQ2G63BFR 1.0GHz Max Min Max Units Notes - 31 - nCK - 1 - nCK - 100 - 512 - nCK - 256 - nCK - 64 - nCK max(5nsC ...
Page 75
... K, 10ns) K, 10ns) max(5nsC max(5nsC - K, 10ns) K, 10ns MAX(10nC MAX(10nC - K,24ns) K,24ns tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI RL+4+1 - RL+4+1 WL+4+(tW WL+4+( tCK(avg)) tCK(avg)) H5TQ2G63BFR 1.0GHz Max Min Max Units Notes max(5nsC - - K, 10ns) max(5nsC - - K, 10ns MAX(10nC - - K,24ns nCK - 1 - nCK - 1 - nCK - RL+4+1 - nCK ...
Page 76
... Min Max Min WL+4+WR WL+4+ WL+2+(tW WL+2+( tCK(avg)) tCK(avg)) WL+2+WR WL+2+ tMOD(min -225 225 -200 0.3 0.7 0.3 0.3 0.7 0 H5TQ2G63BFR 1.0GHz Max Min Max Units Notes WL+4+ nCK +1 WL+2+( nCK tCK(avg)) WL+2+ nCK + nCK - tMOD(min nCK - 6 - nCK 200 -175 175 ps tCK 0 ...
Page 77
... DQS, DQS crossing to tWLH rising CK, CK crossing Write leveling output tWLO delay Write leveling output tWLOE error Rev. 0.5 / Aug. 2010 800MHz 900MHz Min Max Min Max 170 - 130 170 - 130 H5TQ2G63BFR 1.0GHz Min Max Units Notes - 25 - nCK - 120 - ps - 120 - ...
Page 78
... These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous tim- ing holds at all times. (Min and max of SPEC values are to be used for calculations in Table . Rev. 0.5 / Aug. 2010 H5TQ2G63BFR 78 ...
Page 79
... One method for calculating the interval between ZQCS commands, given the temperature (Tdrifrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The interval could be defined by the following formula. Rev. 0.5 / Aug. 2010 H5TQ2G63BFR 79 ...
Page 80
... REF(dc the actual signal is always later than the nominal slew rate line REF(dc) level is used for derating value (see Figure 6). REF(dc) IH/IL(ac) H5TQ2G63BFR C / sec and Vdriftrate = o = 128ms REF(dc region’, the slew rate of a tangent line to the region’, the slew rate of a tangent line to the ...
Page 81
... H5TQ2G63BFR 1.0GHz reference TBD V IH/L(ac) TBD V IH/L(dc) TBD + 125 V IH/L(dc) 1.4 V/ns 1.2 V/ns 1.0 V/ns 66 112 74 120 84 128 - ...
Page 82
... VAC max - - - - - - - - - - H5TQ2G63BFR 1.4 V/ns 1.2 V/ 107 - - -44 -1 - 150 mV [ps] VAC min max 175 170 167 163 162 161 159 155 150 150 1.0 V/ns 115 100 ...
Page 83
... Rev. 0.5 / Aug. 2010 tIS tIH tDS tDH nominal slew rate tVAC max Setup Slew Rate IL(ac) ΔTF Rising Signal for setup time t VAC H5TQ2G63BFR tIS tIH tDH tDS tVAC nominal slew rate VREF to ac region Δ min - V IH(ac) = ΔTR (for DQ with respect to strobe) and ...
Page 84
... Rev. 0.5 / Aug. 2010 tIS tIH tDS tDH REF nominal slew rate Δ max IL(dc) Hold Slew Rate ΔTR Falling Signal (for DQ with respect to strobe) and t DH H5TQ2G63BFR tIS tIH tDH tDS nominal slew rate REF region Δ min - V IH(dc) REF(dc) = ΔTF ...
Page 85
... Setup Slew Rate Rising Signal Δ TF Setup Slew Rate Falling Signal (for DQ with respect to strobe) and t DS H5TQ2G63BFR tIS tIH tDH tDS tVAC line tangent line REF region Δ TR tangent line [V min - V ...
Page 86
... REF tangent line REF Δ max] REF(dc) IL(dc) ΔTR tangent line [V Hold Slew Rate = Falling Signal (for DQ with respect to strobe) and t DH H5TQ2G63BFR tIS tIH tDH tDS nominal line tangent line nominal line ΔTF min - V IH(dc) REF(dc) Δ ...
Page 87
... If the actual signal is REF(dc) level is used for derating value (see figure 9). REF(dc) IH/IL(ac) 900MHz 0 45 H5TQ2G63BFR REF(dc region’, the slew rate of a tangent line to IL(dc) region’, the slew rate of a tangent line to REF(dc) for some time t (see Table 17). ...
Page 88
... V/ns 1.8 V/ns ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS - min > 2.0 75 2.0 57 1.5 50 1.0 38 0.9 34 0.8 29 0.7 22 0.6 13 0.5 0 < 0.5 0 H5TQ2G63BFR a 1.6 V/ns 1.4 V/ns 1.2 V/ns ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH - - - - - - - - - - - - - -11 - -30 -26 t [ps] VAC max - - - - - - - ...
Page 89
... Rev. 0.5 / Aug. 2010 tIS tIH tDS tDH nominal slew rate tVAC max Setup Slew Rate IL(ac) ΔTF Rising Signal for hold setup t VAC H5TQ2G63BFR tIS tIH tDH tDS tVAC nominal slew rate VREF to ac region Δ min - V IH(ac) = ΔTR (for DQ with respect to strobe) and ...
Page 90
... Rev. 0.5 / Aug. 2010 tIS tIH tDS tDH REF nominal slew rate Δ max IL(dc) Hold Slew Rate ΔTR Falling Signal (for DQ with respect to strobe) and t DH H5TQ2G63BFR tIH tIS tDH tDS nominal slew rate REF region Δ min - V IH(dc) REF(dc) = ΔTF ...
Page 91
... Setup Slew Rate Rising Signal Δ TF Setup Slew Rate Falling Signal (for DQ with respect to strobe) and t DS H5TQ2G63BFR tIS tIH tDH tDS tVAC line tangent line REF region Δ TR tangent line [V min - V ...
Page 92
... REF tangent line REF Δ max] REF(dc) IL(dc) ΔTR tangent line [V Hold Slew Rate = Falling Signal (for DQ with respect to strobe) and t DH H5TQ2G63BFR tIS tIH tDH tDS nominal line tangent line nominal line ΔTF min - V IH(dc) REF(dc) Δ ...
Page 93
... Package Dimension(x16); 96Ball Fine Pitch Ball Grid Array Outline A1 CORNER (2.250) INDEX AREA 3.0 X 5.0 MIN FLAT AREA 0.800 6.400 0.800 1.600 x 96 φ0.450 0.050 ± BOTTOM VIEW Rev. 0.5 / Aug. 2010 9.000 0.100 ± TOP VIEW BALL MARK 1.600 H5TQ2G63BFR 1.100 0.100 ± 0.340 0.050 ± SIDE VIEW 93 ...