A25L040O-F AMIC, A25L040O-F Datasheet

58T1309

A25L040O-F

Manufacturer Part Number
A25L040O-F
Description
58T1309
Manufacturer
AMIC
Datasheet

Specifications of A25L040O-F

Memory Type
Flash
Memory Size
4Mbit
Memory Configuration
4M X 1
Interface Type
Serial, SPI
Clock Frequency
100MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
SOIC
No. Of Pins
8
Rohs Compliant
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A25L040O-F
Manufacturer:
AMIC
Quantity:
20 000
Document Title
Revision History
(October, 2010, Version 1.2)
4Mbit, Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors
Rev. No.
1.0
1.1
1.2
History
Initial issue
Add packing description in Part Numbering Scheme
P28: Change D
to Min.
ata Retention and Endurance value from Max.
4Mbit Low Voltage, Serial Flash Memory
With 100MHz Uniform 4KB Sectors
Issue Date
April 10, 2009
May 3, 2010
October 20, 2010
AMIC Technology Corp.
A25L040 Series
Remark
Final

Related parts for A25L040O-F

A25L040O-F Summary of contents

Page 1

... Retention and Endurance value from Max. P28: Change D to Min. (October, 2010, Version 1.2) A25L040 Series 4Mbit Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors Issue Date April 10, 2009 May 3, 2010 October 20, 2010 AMIC Technology Corp. Remark Final ...

Page 2

... The whole memory can be erased using the Chip Erase instruction, a block at a time, using Block Erase instruction sector at a time, using the Sector Erase instruction HOLD DIO 1 A25L040 Series With 100MHz Uniform 4KB Sectors A25L040: (3013h) compatibility A25L040 (12h) DIP8 Connections A25L040 HOLD DIO SS AMIC Technology Corp. ...

Page 3

... Version 1.2) High Voltage Generator I/O Shift Register 256 Byte Data Buffer 00000h 256 Byte (Page Size) X Decoder A25L040 Series Status Register 7FFFFh (4M) Size of the memory area 000FFh Logic Symbol V CC DIO C S A25L040 W HOLD V SS AMIC Technology Corp. DO ...

Page 4

... The main purpose of this input signal is Write Protect ( W to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1, and BP0 bits of the Status Register). AMIC Technology Corp. 3 A25L040 Series required ) signal is used to pause ...

Page 5

... C remains at 0 for (CPOL=0, CPHA=0) – C remains at 1 for (CPOL=1, CPHA= DIO SPI Memory Device S W HOLD HOLD ) signals should be driven, High or Low as appropriate MSB DO 4 A25L040 Series C DO DIO C DO SPI Memory SPI Memory Device Device S W HOLD S MSB AMIC Technology Corp. DIO W HOLD ...

Page 6

... Deep Power-down mode offers extra software protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored except one particular instruction (the instruction). 5 A25L040 Series W ) signal. ) can provide PUW W ) signal allows the Block Protect Release from Deep Power-down AMIC Technology Corp. ...

Page 7

... All blocks Lower seven-eighths (7 blocks Lower three-quarters (6 blocks Lower half (4 blocks None None None None S ) goes High while the device is in the Hold HOLD ) High, and then to drive S ) Low. This prevents the device from going Hold Condition (non-standard use) AMIC Technology Corp ...

Page 8

... AMIC Technology Corp. 7 A25L040 Series 07FFFFh 070FFFh 06FFFFh 060FFFh 05FFFFh 050FFFh 04FFFFh 040FFFh 03FFFFh 030FFFh 02FFFFh 020FFFh 01FFFFh 010FFFh 00FFFFh 003FFFh 002FFFh ...

Page 9

... One-byte Address Dummy Bytes Bytes 06h 0 04h 0 05h 0 01h 0 03h 3 0Bh 3 3Bh 3 (2) BBh 3 02h 3 20h 3 D8h 3 C7h 0 B9h 0 9Fh 0 (3) 90h 1 0 ABh 0 AMIC Technology Corp must be driven S ) must Data Bytes ∞ ∞ ∞ ∞ ( ∞ 256 ∞ ∞ ∞ ...

Page 10

... Write Disable (WRDI) instruction completion ﹣ Write Status Register (WRSR) instruction completion ﹣ Page Program (PP) instruction completion ﹣ Sector Erase (SE) instruction completion ﹣ Bulk Erase (BE) instruction completion Instruction DIO High Impedance DO 9 A25L040 Series S ) Low, sending the instruction code, and then S ) High AMIC Technology Corp. ...

Page 11

... Register (SRWD, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution Status Register Out MSB 10 A25L040 Series W ) signal allow the device to be put in the Status Register Out MSB AMIC Technology Corp signal ...

Page 12

... Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered initiated. While the Instruction 7 High Impedance MSB 11 A25L040 Series Status Register AMIC Technology Corp. ) signal. The Status W ) ...

Page 13

... A25L040 Series Memory Content 1 Protected Area Unprotected Area Ready to accept Page Program, Sector Erase, and Block Erase instructions Ready to accept Page Program, Sector Erase, and Block Erase instructions W ) Low W ) Low after setting the W ) High permanently tied High, the Hardware AMIC Technology Corp. 1 ...

Page 14

... High at any time during data output. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress 24-Bit Address MSB 13 A25L040 Series High. Chip Select ( 0 Data Out 2 Data Out MSB AMIC Technology Corp. ) can be driven ...

Page 15

... Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress Instruction 24-Bit Address MSB Data Out MSB 14 A25L040 Series S ) can be driven High at any time during data Data Out MSB AMIC Technology Corp High. 7 MSB ...

Page 16

... However, the DIO pin should be high-impedance prior to the falling edge of the first data out clock. This Instruction 24-Bit Address MSB DIO switches from input to output MSB Data Out 1 Data Out 2 15 A25L040 Series MSB MSB Data Out 3 Data Out 4 AMIC Technology Corp. ...

Page 17

... However, the DIO and DO pins should be high-impedance prior to the falling edge of the first data out clock. This Instruction 24-Bit Address MSB DIO switches from input to output MSB MSB Data Out 2 Data Out 3 Data Out 1 16 A25L040 Series MSB Data Out 4 Data Out 5 AMIC Technology Corp. 7 MSB ...

Page 18

... Block Protect (BP2, BP1, BP0) bits (see Table 1. and Table 2.) is not executed Instruction 24-Bit Address MSB Data Byte MSB 17 A25L040 Series S ) must be driven High after the eighth bit of the driven High, the self-timed Data Byte MSB Data Byte 256 MSB AMIC Technology Corp initiated. While PP ...

Page 19

... Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see table 1. and table 2.) is not executed Instruction 24-Bit Address MSB 18 A25L040 Series ) is initiated. While the Sector Erase cycle AMIC Technology Corp ...

Page 20

... Write Enable Latch (WEL) bit is reset. A Block Erase (BE) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see table 1. and table 2.) is not executed Instruction MSB 19 A25L040 Series ) is initiated. While the Block Erase cycle is in progress 24-Bit Address AMIC Technology Corp ...

Page 21

... The Chip Erase (CE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The Chip Erase (CE) instruction is ignored if one, or more, blocks are protected Instruction Note: Address bits A23 to A19 are Don’t Care, for A25L040. 20 A25L040 Series driven High AMIC Technology Corp. ...

Page 22

... Instruction Stand-by Mode 21 A25L040 Series S ) Low, followed by the instruction code must be driven Low S ) must be driven High after the eighth bit of the driven High, it requires a delay Deep Power-down Mode AMIC Technology Corp. DP and the Deep CC2 ...

Page 23

... Low. and execute instructions. Device Identification Memory Type 30h Manufacture ID Memory Type 22 A25L040 Series S ) High at any time during data output driven High, the device is put in the Memory Capacity 13h (A25L040 Memory Capacity AMIC Technology Corp. ...

Page 24

... The manufacturer identification is assigned by JEDEC, and has the value 37h for AMIC. The device identification is assigned by the device manufacturer, and has the value 12h for A25L040. Any Read Electronic Manufacturer ID & Device ID (REMS) ...

Page 25

... Dummy Bytes MSB MSB Deep Power-down Mode 24 A25L040 Series ) High after the Electronic Signature has been read driven Low, cause the driven High, the device is put in the , and Chip Select ( RES2 (max), as specified in AC RES2 t RES2 Stand-by Mode AMIC Technology Corp ...

Page 26

... Stand-by Power mode is delayed by t and Chip Select ( as specified in AC Characteristics Table. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. 25 A25L040 Series RES1 Stand-by Mode S ) must remain High for at least t AMIC Technology Corp. , RES1 (max), RES1 ...

Page 27

... The device is in the Standby mode (not the Deep Power-down mode). The Write Enable Latch (WEL) bit is reset. feed. Each device in a system should CC rail decoupled by a suitable capacitor close to CC drops from the operating voltage, CC Full Device Access time AMIC Technology Corp. has risen above CC , all operations are WI ...

Page 28

... INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). (October, 2010, Version 1.2) Parameter 27 A25L040 Series Min. Max. Unit 2 AMIC Technology Corp. ...

Page 29

... Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the AMIC SURE Program and other relevant quality docu- ments. Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their ...

Page 30

... DO = open 1.6mA –100µA OH Parameter Parameter 29 A25L040 Series Min. Max –0.5 0.3V 0. –0.2 CC Min. Typ. Max 0.2 0.24 0.5 1 Min. Max 0. 0. AMIC Technology Corp. Unit ± 2 µA ± 2 µA 25 µA 25 µ +0 Unit Unit ...

Page 31

... Figure 22. AC Measurement I/O Waveform 0.8V 0.2V (October, 2010, Version 1.2) Input Levels A25L040 Series Input and Output Timing Reference Levels 0.7V CC 0.5V CC 0.3V CC AMIC Technology Corp. ...

Page 32

... Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. (October, 2010, Version 1.2) Parameter 3 (peak to peak) 3 (peak to peak A25L040 Series Min. Typ. Max. Unit D.C. 100 MHz D.C. 50 MHz 0.1 V/ns 0.1 V/ 100 100 ns 3 µs 30 µs 30 µ 0.2 0.24 s 0.5 1 AMIC Technology Corp. ...

Page 33

... Figure 23. Serial Input Timing S tCHSL C tDVCH DIO DO Figure 24. Write Protect Setup and Hold Timing during WRSR when SRWD=1 W tWHSL S C DIO DO (October, 2010, Version 1.2) tSLCH tCHDX MSB IN High Impedance High Impedance 32 A25L040 Series tSHSL tSHCH tCHSH tCHCL tCLCH LSB IN tSHWL AMIC Technology Corp. ...

Page 34

... Hold Timing Figure 25 DIO DO HOLD Figure 26. Output Timing S C DIO ADDR.LSB IN tCLQV tCLQX tCLQX DO (October, 2010, Version 1.2) tHLCH tCHHL tCHHH tHLQZ tCH tCLQV 33 A25L040 Series tHHCH tHHQX tCL LSB OUT tQLQH tQHQL AMIC Technology Corp. tSHQZ ...

Page 35

... Mbit (4KB uniform sectors) 020 = 2 Mbit (4KB uniform sectors) 040 = 4 Mbit (4KB uniform sectors) 080 = 8 Mbit (4KB uniform sectors) 016 = 16 Mbit (4KB uniform sectors) 032 = 32 Mbit (4KB uniform sectors) Device Voltage L = 2.7-3.6V Device Type A25 = AMIC Serial Flash AMIC Technology Corp. ...

Page 36

... Ordering Information Part No. Speed (MHz) A25L040-F A25L040O-F A25L040O-UF 100 A25L040M-F A25L040M- for industrial operating temperature range: -40°C ~ +85°C Blank is for commercial operating temperature range: 0 ° +70 ° C (October, 2010, Version 1.2) Active Read Program/Erase Current Current Max. (mA) Max. (mA A25L040 Series Standby Current Package Max. (μ ...

Page 37

... Dimensions in mm Min Nom Max - - 4.57 0. 3.25 3.30 3.45 0.36 0.46 0.56 1.27 1.52 1.78 0.81 0.99 1.17 0.20 0.25 0.33 8.89 9.14 9.40 7.37 7.62 8.00 6.45 6.60 6.76 - 2. 8.76 - 9.78 0.41 0.53 0.66 AMIC Technology Corp. unit: inches/mm ...

Page 38

... Dimensions in mm Symbol A 1.35~1.75 A 0.10~0. 0.33~0.51 D 4.7~5.0 E 3.80~4.00 e 1.27 BSC H 5.80~6. 0.40~1.27 Notes: 1. Maximum allowable mold flash is 0.15mm. 2. Complies with JEDEC publication 95 MS –012 AA. 3. All linear dimensions are in millimeters (max/min). 4. Coplanarity: Max. 0.1mm 37 A25L040 Series L AMIC Technology Corp. unit: mm ...

Page 39

... E 7.70 7.90 E 5.18 5. 1.27 BSC L 0.50 0.65 θ 0° - Notes: Maximum allowable mold flash is 0.15mm at the package ends and 0.25mm between leads 38 A25L040 Series C θ L Max 2.16 0.25 1.91 0.48 0.25 5.33 8.10 5.38 0.80 8° AMIC Technology Corp. unit: mm ...

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