PALCE16V8Z-25PI Lattice, PALCE16V8Z-25PI Datasheet - Page 2

• Manufacturer Part Number: PALCE16V8Z-25PI
• Description: SPLD PAL® Family 8 Macro Cells 50MHz EECMOS Technology 5V 20-Pin PDIP
• Manufacturer: Lattice

Specifications of PALCE16V8Z-25PI

• Package: 20PDIP
• Family Name: PAL®
• Maximum Propagation Delay Time: 25 ns
• Typical Operating Supply Voltage: 5 V
• Maximum Internal Frequency: 50 MHz
• Number Of Product Terms Per Macro: 8
• Re-programmability Support: Yes

BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
The PALCE16V8 is a universal PAL device. The PALCE16V8Z is the zero-power version of the
PALCE16V8. It has all the architectural features of the PALCE16V8. In addition, the PALCE16V8Z
has zero standby power and an unused product term disable feature for reduced power
consumption. It has eight independently configurable macrocells (MC
be configured as registered output, combinatorial output, combinatorial I/O or dedicated input.
The programming matrix implements a programmable AND logic array, which drives a fixed OR
logic array. Buffers for device inputs have complementary outputs to provide user-
programmable input signal polarity. Pins 1 and 11 serve either as array inputs or as clock (CLK)
and output enable (OE), respectively, for all flip-flops.
Unused input pins should be tied directly to V
unprogrammed (disconnected) assume the logical HIGH state, and product terms with both true
and complement of any input signal connected assume a logical LOW state.
The programmable functions on the PALCE16V8 are automatically configured from the user’s
design specification. The design specification is processed by development software to verify
the design and create a programming file (JEDEC). This file, once downloaded to a programmer,
configures the device according to the user’s desired function.
The user is given two design options with the PALCE16V8. First, it can be programmed as a
standard PAL device from the PAL16R8 series. The PAL programmer manufacturer will supply
device codes for the standard PAL device architectures to be used with the PALCE16V8.
The programmer will program the PALCE16V8 in the corresponding architecture. This allows
the user to use existing standard PAL device JEDEC files without making any changes to them.
2
OE
/I
9
MACRO
MC
I/O
0
0
MACRO
MC
I/O
1
1
MACRO
MC
I/O
PALCE16V8 and PALCE16V8Z Families
2
2
Programmable AND Array
MACRO
MC
I/O
3
3
32 x 64
I 1 – I 8
8
CC
MACRO
MC
or GND. Product terms with all bits
I/O
4
4
MACRO
MC
I/O
5
5
0
MACRO
MC
-
I/O
MC
6
6
7
). Each macrocell can
MACRO
MC
I/O
7
7
CLK/I 0
16493E-1