PALCE16V8Z-25PI Lattice, PALCE16V8Z-25PI Datasheet - Page 29

• Manufacturer Part Number: PALCE16V8Z-25PI
• Description: SPLD PAL® Family 8 Macro Cells 50MHz EECMOS Technology 5V 20-Pin PDIP
• Manufacturer: Lattice

Specifications of PALCE16V8Z-25PI

• Package: 20PDIP
• Family Name: PAL®
• Maximum Propagation Delay Time: 25 ns
• Typical Operating Supply Voltage: 5 V
• Maximum Internal Frequency: 50 MHz
• Number Of Product Terms Per Macro: 8
• Re-programmability Support: Yes

INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR PALCE16V8Z
POWER-UP RESET
The PALCE16V8 has been designed with the capability to reset during system power-up.
Following power-up, all flip-flops will be reset to LOW. The output state will be HIGH
independent of the logic polarity. This feature provides extra flexibility to the designer and is
especially valuable in simplifying state machine initialization. A timing diagram and parameter
table are shown below. Due to the synchronous operation of the power-up reset and the wide
range of ways V
power-up reset. These conditions are:
t
t
t
PR
S
WL
Parameter Symbol
The V
Following reset, the clock input must not be driven from LOW to HIGH until all applicable input
and feedback setup times are met.
CC
rise must be monotonic.
CC
Power-Up Reset Time
Input or Feedback Setup Time
Clock Width LOW
Protection
Clamping
can rise to its steady state, two conditions are required to ensure a valid
ESD
and
Transition
Detection
Parameter Descriptions
Input
PALCE16V8 and PALCE16V8Z Families
Programming
Pins Only
Provides ESD
Protection and
Clamping
V
CC
Typical Output
Typical Input
V
Programming
CC
Detection
Circuitry
Preload
Voltage
Feedback
Input
Min
Overshoot
Positive
Filter
Transition
Detection
Input
See Switching Characteristics
Max
1000
Programming
Circuitry
Unit
ns
16493E-11
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