PALCE16V8Z-25PI Lattice, PALCE16V8Z-25PI Datasheet - Page 4

• Manufacturer Part Number: PALCE16V8Z-25PI
• Description: SPLD PAL® Family 8 Macro Cells 50MHz EECMOS Technology 5V 20-Pin PDIP
• Manufacturer: Lattice

Specifications of PALCE16V8Z-25PI

• Package: 20PDIP
• Family Name: PAL®
• Maximum Propagation Delay Time: 25 ns
• Typical Operating Supply Voltage: 5 V
• Maximum Internal Frequency: 50 MHz
• Number Of Product Terms Per Macro: 8
• Re-programmability Support: Yes

Registered Output Configuration
The control bit settings are SG0 = 0, SG1 = 1 and SL0
configuration. All eight product terms are available as inputs to the OR gate. Data polarity is
determined by SL1
path is from Q on the register. The output buffer is enabled by OE.
Combinatorial Configurations
The PALCE16V8 has three combinatorial output configurations: dedicated output in a non-
registered device, I/O in a non-registered device and I/O in a registered device.
Dedicated Output in a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0
to the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the
exception of pins 15 and 16. Pins 15 and 16 do not use feedback in this mode. Because CLK
and OE are not used in a non-registered device, pins 1 and 11 are available as input signals. Pin
1 will use the feedback path of MC
Combinatorial I/O in a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 1, and SL0
available to the OR gate. The eighth product term is used to enable the output buffer. The signal
at the I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to
be used as an input.
Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as
inputs. Pin 1 will use the feedback path of MC
Combinatorial I/O in a Registered Device
The control bit settings are SG0 = 0, SG1 = 1 and SL0
to the OR gate. The eighth product term is used as the output enable. The feedback signal is the
corresponding I/O signal.
Dedicated Input Configuration
The control bit settings are SG0 = 1, SG1 = 0 and SL0
for MC
are pins 1 and 11. These configurations are summarized in Table 1 and illustrated in Figure 2.
4
SG0
0
0
0
and MC
SG1
1
1
SL0 X
7
Device Uses Registers
0
1
, the feedback signal is an adjacent I/O. For MC
x.
The flip-flop is loaded on the LOW-to-HIGH transition of CLK. The feedback
Registered Output
Configuration
Combinatorial
Cell
I/O
PALCE16V8 and PALCE16V8Z Families
Table 1. Macrocell Configuration
7
PAL16R8, 16R6,
, and pin 11 will use the feedback path of MC
PAL16R6, 16R4
Emulated
Devices
16R4
7
, and pin 11 will use the feedback path of MC
SG0
1
1
1
x
x
= 1. Only seven product terms are available
x
x
= 1. The output buffer is disabled. Except
x
= 0. All eight product terms are available
= 0. There is only one registered
= 1. Only seven product terms are
SG1
0
0
1
Device Uses No Registers
SL0 X
0
0
1
1
and MC
Configuration
Combinatorial
Combinatorial
7
Output
Input
, the feedback signals
Cell
I/O
0
14H4, 16H2, 10L8,
16H2, 12L6, 14L4,
.
12L6, 14L4, 16L2
PAL10H8, 12H6,
PAL12H6, 14H4,
Emulated
Devices
PAL16L8
16L2
0
.