PALCE16V8Z-25PI Lattice, PALCE16V8Z-25PI Datasheet - Page 9

• Manufacturer Part Number: PALCE16V8Z-25PI
• Description: SPLD PAL® Family 8 Macro Cells 50MHz EECMOS Technology 5V 20-Pin PDIP
• Manufacturer: Lattice

Specifications of PALCE16V8Z-25PI

• Package: 20PDIP
• Family Name: PAL®
• Maximum Propagation Delay Time: 25 ns
• Typical Operating Supply Voltage: 5 V
• Maximum Internal Frequency: 50 MHz
• Number Of Product Terms Per Macro: 8
• Re-programmability Support: Yes

LOGIC DIAGRAM
CLK/I 0 1
I 1
I 2
I 3 4
I 4
2
3
5
15
16
23
24
31
0
7
8
0
0
3 4
3 4
7 8
7 8
11 12
11 12 15 16 19 20
15 16 19 20
PALCE16V8 and PALCE16V8Z Families
23
23 24 27 28 31
24 27 28
31
0 X
1 1
0 X
1 0
1 1
1 0
0 X
1 0
1 1
0 X
1 0
1 1
SL1
SG1
SG1
SL1
SL1
SL1
SG1
SG1
6
4
5
7
SL0
SL0
SL0
SL0
CLK OE
7
6
5
4
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
V CC
V CC
V CC
V CC
SG1
SG1
SG1
SG0
0 X
1 0
1 1
0 X
0 X
1 0
0 X
1 1
1 0
0 0
0 1
1 1
1 0
1 1
1 0
0 0
0 1
1 1
0 X
1 0
1 0
1 1
1 1
1 0
0 0
0 1
1 1
0 X
1 0
1 1
0 X
1 0
0 X
1 1
1 0
0 0
0 1
1 1
1 0
1 1
SL0
SL0
SL0
SL0
7
6
5
4
16493E-2
20 V
19
18
16
17
I/O
I/O 6
CC
I/O 4
I/O 5
7
9