DAC1210LCJ-1 National Semiconductor, DAC1210LCJ-1 Datasheet - Page 5

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DAC1210LCJ-1

Manufacturer Part Number
DAC1210LCJ-1
Description
DAC 1-CH R-2R 12-Bit 24-Pin CDIP
Manufacturer
National Semiconductor
Datasheet

Specifications of DAC1210LCJ-1

Package
24CDIP
Resolution
12 Bit
Architecture
R-2R
Digital Interface Type
Parallel
Number Of Outputs Per Chip
1
Output Type
Current
Full Scale Error
-0.2 %FSR
Integral Nonlinearity Error
±0.05 %FSR
Maximum Settling Time
1(Typ) us

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Definition of Package Pinouts
CONTROL SIGNALS (all control signals are level actuated)
CS Chip Select (active low) The CS will enable WR1
WR1 Write 1 The active low WR1 is used to load the digital
data bits (DI) into the input latch The data in the input latch
is latched when WR1 is high The 12-bit input latch is split
into two latches One holds the first 8 bits while the other
holds 4 bits The Byte 1 Byte 2 control pin is used to select
both latches when Byte 1 Byte 2 is high or to overwrite the
4-bit input latch when in the low state
Byte 1 Byte 2 Byte Sequence Control When this control is
high all 12 locations of the input latch are enabled When
low only the four least significant locations of the input latch
are enabled
WR2 Write 2 (active low) The WR2 will enable XFER
XFER Transfer Control Signal (active low) This signal in
combination with WR2 causes the 12-bit data which is
available in the input latches to transfer to the DAC register
DI
input (LSB) and DI
(MSB)
I
digital code of all 1s in the DAC register and is zero for all
0s in the DAC register
I
I
voltage) This constant current is
divided by the reference input resistance
R
on the IC chip for use as the shunt feedback resistor for the
external op amp which is used to provide an output voltage
for the DAC This on-chip resistor should always be used
(not an external resistor) since it matches the resistors in
the on-chip R-2R ladder and tracks these resistors over
temperature
V
ternal precision voltage source to the internal R-2R ladder
V
is also the analog voltage input for a 4-quadrant multiplying
DAC application
V
the part V
optimum for 15 V
GND Pins 3 and 12 of the DAC1208 DAC1209 and
DAC1210 must be connected to ground Pins 3 and 10 of
OUT1
OUT1
OUT2
REF
Fb
REF
CC
0
to DI
Feedback Resistor The feedback resistor is provided
Digital Supply Voltage This is the power supply pin for
can be selected over the range of 10V to
Reference Voltage Input This input connects an ex-
DAC Current Output 1 I
DAC Current Output 2 I
or I
11
CC
OUT1
Digital Inputs DI
can be from 5 V
a) End Point Test After Zero
a
DC
I
OUT2
11
V
REF c
and FS Adjust
is the most significant digital input
e
constant (for a fixed reference
0
1
is the least significant digital
DC
b
OUT1
OUT2
4096
to 15 V
1
is a maximum for a
is a constant minus
DC
Operation is
b
10V This
5
DAC transfer characteristic It is measured after adjusting
the DAC1230 DAC1231 and DAC1232 must be connected
to ground It is important that I
potential for current switching applications Any difference
of potential (V
change of
For example if V
mV offset from I
0 03%
Definition of Terms
Resolution Resolution is defined as the reciprocal of the
number of discrete steps in the DAC output It is directly
related to the number of switches or bits within the DAC For
example the DAC1208 has 2
has 12-bit resolution
Linearity Error Linearity error is the maximum deviation
from a straight line passing through the endpoints of the
for zero and full-scale Linearity error is a parameter intrinsic
to the device and cannot be externally adjusted
National’s linearity test (a) and the best straight line test (b)
used by other suppliers are illustrated below The best
straight line (b) requires a special zero and FS adjustment
for each part which is almost impossible for the user to
determine The end point test uses a standard zero FS ad-
justment procedure and is a much more stringent test for
DAC linearity
Power Supply Sensitivity Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output
Settling Time Full-scale current settling time requires zero
to full-scale or full-scale to zero output change Settling time
is the time required from a code transition until the DAC
output reaches within
Full-Scale Error Full-scale error is a measure of the output
error between an ideal DAC and the actual device output
Ideally for the DAC1208 or DAC1230 series full-scale is
V
V
error is adjustable to zero
Differential Non-Linearity The difference between any
two consecutive codes in the transfer curve from the theo-
retical 1 LSB is differential non-linearity
Monotonic If the output of a DAC increases for increasing
digital input code then the DAC is monotonic A 12-bit DAC
which is monotonic to 12 bits simply means that input in-
creasing digital input codes will produce an increasing ana-
log output
REF
FULL-SCALE
b
1 LSB For V
e
b) Shifting FS Adjust to Pass
OS
10 0000V
OUT 1
REF
Best Straight Line Test
on these pins) will result in a linearity
and I
e
g
REF
b
10V and these ground pins are 9
3 V
OUT 2
e
2 44 mV
LSB of the final output value
V
OS
12
10V and unipolar operation
REF
OUT 1
or 4096 steps and therefore
the linearity change will be
and I
e
9 9976V
OUT 2
are at ground
TL H 5690– 5
Full-scale

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