CY7C109B-20VI Cypress Semiconductor Corp, CY7C109B-20VI Datasheet

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CY7C109B-20VI

Manufacturer Part Number
CY7C109B-20VI
Description
SRAM Chip Async Single 5V 1M-Bit 128K x 8 20ns 32-Pin SOJ
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C109B-20VI

Package
32SOJ
Timing Type
Asynchronous
Density
1 Mb
Typical Operating Supply Voltage
5 V
Address Bus Width
17 Bit
Number Of I/o Lines
8 Bit
Number Of Ports
1
Number Of Words
128K

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C109B-20VI
Quantity:
200
Cypress Semiconductor Corporation
Document #: 38-05038 Rev. *A
Features
Functional Description
The CY7C109B / CY7C1009B is a high-performance CMOS
static RAM organized as 131,072 words by 8 bits. Easy mem-
ory expansion is provided by an active LOW Chip Enable
(CE
Selection Guide
Note:
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Maximum CMOS Standby Current (mA)
Low Power Version
1.
• High speed
• Low active power
• Low CMOS standby power
• 2.0V Data Retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
CE
CE
WE
OE
Logic Block Diagram
— t
— 495 mW (max. 12 ns)
— 55 mW (max.) 4 mW
1
2
1
For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
), an active HIGH Chip Enable (CE
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
AA
= 12 ns
INPUT BUFFER
512 x 256 x 8
DECODER
COLUMN
ARRAY
[1]
1
POWER
DOWN
, CE
2
), an active LOW Out-
2
, and OE options
7C1009B-12
7C109B-12
3901 North First Street
12
90
10
2
7C1009B-15
7C109B-15
put Enable (OE), and three-state drivers. Writing to the device
is accomplished by taking Chip Enable One (CE
Enable (WE) inputs LOW and Chip Enable Two (CE
HIGH. Data on the eight I/O pins (I/O
written into the location specified on the address pins (A
through A
Reading from the device is accomplished by taking Chip En-
able One (CE
Write Enable (WE) and Chip Enable Two (CE
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH or CE
during a write operation (CE
The CY7C109B is available in standard 400-mil-wide SOJ and
32-pin TSOP type I packages. The CY7C1009B is available in
a 300-mil-wide SOJ package. The CY7C1009B and
CY7C109B are functionally equivalent in all other respects.
15
80
10
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2
0
1
2
3
4
5
6
7
CE
V
A
A
WE
A
A
A
A
NC
CC
A
A
A
A
A
A
11
13
15
16
14
12
9
8
2
7
6
5
4
16
San Jose
).
2
7C1009B-20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
7C109B-20
LOW), the outputs are disabled (OE HIGH), or
1
) and Output Enable (OE) LOW while forcing
20
75
10
2
128K x 8 Static RAM
Pin Configurations
GND
I/O
I/O
I/O
A
A
A
NC
A
A
A
A
A
A
A
A
16
14
12
7
6
5
4
3
2
1
0
0
1
2
(not to scale)
1
CA 95134
Top View
LOW, CE
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
7C1009B-25
TSOP I
7C109B-25
0
SOJ
Revised September 13, 2002
through I/O
25
70
10
-
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
0
CY7C1009B
HIGH, and WE LOW).
CE
A
CE
I/O
I/O
I/O
I/O
I/O
through I/O
V
A
WE
A
A
A
OE
A
10
CC
15
13
8
9
11
CY7C109B
7
6
5
4
3
2
1
109B–2
7
) are placed in a
2
7C1009B-35
408-943-2600
) HIGH. Under
7C109B-35
1
) and Write
35
60
10
7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
-
) is then
2
) input
OE
A
CE
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
A
A
A
A
10
0
1
2
3
7
6
5
4
3
2
1
0
0
1

Related parts for CY7C109B-20VI

CY7C109B-20VI Summary of contents

Page 1

... CE , and OE options 1 2 HIGH or CE during a write operation (CE The CY7C109B is available in standard 400-mil-wide SOJ and 32-pin TSOP type I packages. The CY7C1009B is available in a 300-mil-wide SOJ package. The CY7C1009B and CY7C109B are functionally equivalent in all other respects active LOW Out- 2 I/O ...

Page 2

... Max > < > < MAX Max > V – 0.3V < 0.3V > V – 0.3V < 0.3V CY7C109B CY7C1009B Ambient Temperature + +85 C 7C109B-12 7C109B-15 7C1009B-12 7C1009B-15 Max. Min. 2.4 2.4 0.4 2 0.3 0.8 –0.3 –1 +1 –1 –5 +5 –5 –300 10% 5V 10% Max. Unit V 0.4 ...

Page 3

... V > V – 0.3V < 0.3V Test Conditions MHz 5. 480 5V R2 GND 5 pF 255 INCLUDING JIG AND SCOPE (b) 1.73V CY7C109B CY7C1009B 7C109B-20 7C109B-25 7C109B-35 7C1009B-25 7C1009B-35 Max. Min. Max. Min. 2.4 2.4 2.4 0.4 0.4 2.2 V 2 0.3 + 0.3 0.8 –0.3 0.8 – ...

Page 4

... HIGH to Data 2 0 [7] HIGH to Low [6, 7] LOW to High Z 2 HIGH LOW HIGH to Write End less than less than t HZCE LZCE HZOE LZOE LOW, CE HIGH, and WE LOW CY7C109B CY7C1009B 7C109B-15 7C1009B-15 Max. Min. Max and t is less than t for any given device. ...

Page 5

... HIGH to Data 2 0 [7] HIGH to Low [6, 7] LOW to High Z 2 HIGH LOW HIGH to Write End Over the Operating Range (Low Power version only) Conditions No input may exceed 2.0V > V – 0. > V – 0. CY7C109B CY7C1009B 7C109B-25 7C109B-35 7C1009B-25 7C1009B-35 Min. Max. Min. Min ...

Page 6

... WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE Document #: 38-05038 Rev. *A DATA RETENTION MODE 4.5V V > CDR OHA ACE t DOE t LZOE 50 transition LOW and CE transition HIGH CY7C109B CY7C1009B 4. DATA VALID t HZOE t HZCE IMPEDANCE DATA VALID t PD 50% HIGH Page ...

Page 7

... LOW simultaneously with WE going HIGH, the output remains in a high-impedance state 15. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05038 Rev. *A [13, 14 SCE SCE PWE t SD DATA VALID [13, 14 SCE t SCE PWE t SD DATA VALID IN CY7C109B CY7C1009B Page ...

Page 8

... DATA I/O Truth Table High High Data Out Data High Z Document #: 38-05038 Rev. *A [14 SCE t SCE PWE t HZWE I/O –I Power-Down Power-Down Read Write Selected, Outputs Disabled CY7C109B CY7C1009B DATA VALID t LZWE Mode Power Standby (I Standby (I Active (I CC Active (I CC Active ( Page ...

Page 9

... Ordering Code 12 CY7C109B-12VC CY7C1009B-12VC CY7C109B-12ZC 15 CY7C109B-15VC CY7C109BL-15VC CY7C1009B-15VC CY7C109B-15ZC CY7C109BL-15ZC CY7C109B-15VI CY7C109BL-15VI CY7C1009B-15VI CY7C109B-15ZI 20 CY7C109B-20VC CY7C1009B-20VC CY7C109B-20VI CY7C109B-20ZC CY7C109B-20ZI 25 CY7C109B-25VC CY7C1009B-25VC CY7C109B-25VI CY7C109B-25ZC CY7C109B-25ZI 35 CY7C109B-35VC CY7C1009B-35VC CY7C109B-35VI Document #: 38-05038 Rev. *A Package Name Package Type V33 32-Lead (400-Mil) Molded SOJ V32 ...

Page 10

... Package Diagrams Document #: 38-05038 Rev. *A 32-Lead (300-Mil) Molded SOJ V32 32-Lead (400-Mil) Molded SOJ V33 CY7C109B CY7C1009B 51-85041-*A 51-85033-*B Page ...

Page 11

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C109B CY7C1009B ...

Page 12

... Document History Page Document Title: CY7C109B, CY7C1009 128K x 8 SRAM Document Number: 38-05038 Issue REV. ECN NO. Date ** 106832 09/22/01 *A 116467 09/16/02 Document #: 38-05038 Rev. *A Orig. of Change Description of Change SZV Change from Spec number: 38-00971 to 38-05038 CEA Add applications foot note to data sheet, page 1 ...

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