CY7C421-15VI Cypress Semiconductor Corp, CY7C421-15VI Datasheet

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CY7C421-15VI

Manufacturer Part Number
CY7C421-15VI
Description
FIFO Mem Async Dual Depth/Width Uni-Dir 512 x 9 28-Pin SOJ
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C421-15VI

Package
28SOJ
Configuration
Dual
Bus Directional
Uni-Directional
Density
4.5 Kb
Organization
512x9
Data Bus Width
9 Bit
Timing Type
Asynchronous
Expansion Type
Depth|Width
Typical Operating Supply Voltage
5 V
Operating Temperature
-40 to 85 °C
Cypress Semiconductor Corporation
Document #: 38-06001 Rev. *B
Features
Functional Description
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, and
CY7C432/3 are first-in first-out (FIFO) memories offered in
CY7C419/21/25/29/33256/512/1K/2K/4K x 9 Asynchronous FIFO
• Asynchronous first-in first-out (FIFO) buffer memories
• 256 x 9 (CY7C419)
• 512 x 9 (CY7C421)
• 1K x 9 (CY7C425)
• 2K x 9 (CY7C429)
• 4K x 9 (CY7C433)
• Dual-ported RAM cell
• High-speed 50.0-MHz read/write independent of
• Low operating power: I
• Empty and Full flags (Half Full flag in standalone)
• TTL compatible
• Retransmit in standalone
• Expandable in width
• PLCC, 7x7 TQFP, SOJ, 300-mil and 600-mil DIP
• Pb-Free Packages Available
• Pin compatible and functionally equivalent to IDT7200,
depth/width
IDT7201, IDT7202, IDT7203, IDT7204, AM7200, AM7201,
AM7202, AM7203, and AM7204
CC
= 35 mA
256/512/1K/2K/4K x 9 Asynchronous FIFO
3901 North First Street
600-mil wide and 300-mil wide packages. They are, respec-
tively, 256, 512, 1,024, 2,048, and 4,096 words by 9-bits wide.
Each FIFO memory is organized such that the data is read in
the same sequential order that it was written. Full and Empty
flags are provided to prevent overrun and underrun. Three
additional pins are also provided to facilitate unlimited
expansion in width, depth, or both. The depth expansion
technique steers the control signals from one device to
another in parallel, thus eliminating the serial addition of
propagation delays, so that throughput is not reduced. Data is
steered in a similar manner.
The read and write operations may be asynchronous; each
can occur at a rate of 50.0 MHz. The write operation occurs
when the write (W) signal is LOW. Read occurs when read (R)
goes LOW. The nine data outputs go to the high-impedance
state when R is HIGH.
A Half Full (HF) output flag is provided that is valid in the
standalone and width expansion configurations. In the depth
expansion configuration, this pin provides the expansion out
(XO) information that is used to tell the next FIFO that it will be
activated.
In the standalone and width expansion configurations, a LOW
on the retransmit (RT) input causes the FIFOs to retransmit
the data. Read enable (R) and write enable (W) must both be
HIGH during retransmit, and then R is used to access the data.
The CY7C419, CY7C420, CY7C421, CY7C424, CY7C425,
CY7C428, CY7C429, CY7C432, and CY7C433 are fabricated
using an advanced 0.65-micron P-well CMOS technology.
Input ESD protection is greater than 2000V and latch-up is
prevented by careful layout and guard rings.
San Jose
,
CA 95134
CY7C419/21/25/29/33
Revised June 30, 2005
408-943-2600
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Related parts for CY7C421-15VI

CY7C421-15VI Summary of contents

Page 1

... FIFOs to retransmit the data. Read enable (R) and write enable (W) must both be HIGH during retransmit, and then R is used to access the data. The CY7C419, CY7C420, CY7C421, CY7C424, CY7C425, CY7C428, CY7C429, CY7C432, and CY7C433 are fabricated using an advanced 0.65-micron P-well CMOS technology. ...

Page 2

Logic Block Diagram DATA INPUTS WRITE W RAM ARRAY CONTROL WRITE POINTER THREE- STATE BUFFERS DATA OUTPUTS (Q 0 – READ R CONTROL FLAG LOGIC EXPANSION LOGIC XI Selection Guide 256 x 9 7C419–10 512 x 9 (600-mil ...

Page 3

Operating Range Range Ambient Temperature ° ° Commercial ° ° Industrial – +85 C ° ° Military – +125 C Electrical Characteristics Over the Operating Range Parameter Description V Output ...

Page 4

Electrical Characteristics Over the Operating Range Parameter Description I Operating Current Operating Current V CC1 MHz I Standby Current All Inputs = SB1 V I Power-Down Current All Inputs ...

Page 5

Switching Characteristics Over the Operating Range Parameter Description t Read Cycle Time RC t Access Time A t Read Recovery Time RR t Read Pulse Width PR [6,9] t Read LOW to Low Z LZR [9,10] t Data Valid After ...

Page 6

Switching Characteristics Over the Operating Range Parameter Description LOW EFL HIGH HFH HIGH FFH t Read LOW to EF LOW REF t Read HIGH to FF HIGH RFF ...

Page 7

Switching Characteristics Over the Operating Range Parameter Description t Read Cycle Time RC t Access Time A t Read Recovery Time RR t Read Pulse Width PR [6,9] t Read LOW to Low Z LZR [9,10] t Data Valid After ...

Page 8

Switching Waveforms Asynchronous Read and Write LZR Q – – Master Reset MR [11 Half-full Flag HALF FULL Notes: 11. ...

Page 9

Switching Waveforms (continued) Last Write to First Read Full Flag LAST WRITE WFF FF Last Read to First Write Empty Flag LAST READ REF VALID DATA OUT [13] Retransmit FL/RT R,W ...

Page 10

Switching Waveforms (continued) Empty Flag and Read Data Flow-through Mode DATA DATA OUT Full Flag and Write Data Flow-through Mode DATA DATA OUT DATA VALID Document #: 38-06001 Rev. *B ...

Page 11

Switching Waveforms (continued) Expansion Timing Diagrams WRITE TO LAST PHYSICAL LOCATION OF DEVICE XOL [15 – READ FROM LAST PHYSICAL LOCATION OF DEVICE XOL [15] XO ...

Page 12

FIFO is filled to half its capacity plus one word. HF will remain LOW while less than one half of total memory is available for writing. The LOW-to-HIGH transition of HF occurs t the rising edge of R when the ...

Page 13

FULL MR Document #: 38-06001 Rev CY7C419 9 CY7C420/1 CY7C424/5 CY7C428/9 CY7C432 CY7C419 9 CY7C420/1 CY7C424/5 CY7C428/9 CY7C432 CY7C419 9 CY7C420/1 CY7C424/5 ...

Page 14

... CY7C421–10PC CY7C421–10VC 15 CY7C421–15AC CY7C421–15AXC CY7C421–15JC CY7C421–15JI CY7C421–15VI CY7C421–15DMB CY7C421–15LMB 20 CY7C421–20JC CY7C421–20JXC CY7C421–20PC CY7C421–20VC CY7C421–20VXC CY7C421–20JI Document #: 38-06001 Rev. *B Package Type Package Type A32 32-Pin Thin Plastic Quad Flatpack ...

Page 15

... CY7C421–25JI CY7C421–25PI CY7C421–25DMB 30 CY7C421–30JC CY7C421–30PC CY7C421–30JI CY7C421–30DMB CY7C421–30LMB 40 CY7C421–40JC CY7C421–40PC CY7C421–40VC CY7C421–40JI 65 CY7C421–65JC CY7C421–65PC CY7C421–65VC CY7C421–65JI CY7C421–65DMB Ordering Information (continued) Speed (ns) Ordering Code 40 CY7C424–40PC 65 CY7C424– ...

Page 16

Ordering Information (continued) Speed (ns) Ordering Code 20 CY7C425–20JC CY7C425–20JXC CY7C425–20PC CY7C425–20VC CY7C425–20VXC 25 CY7C425–25JC CY7C425–25PC CY7C425–25JI CY7C425–25VI CY7C425–25DMB CY7C425–25LMB 30 CY7C425–30JC CY7C425–30PC CY7C425–30VC CY7C425–30VI 40 CY7C425–40JC CY7C425–40PC CY7C425–40VC CY7C425–40JI 65 CY7C425–65JC CY7C425–65PC Ordering Information (continued) Speed (ns) Ordering Code ...

Page 17

Ordering Information (continued) Speed (ns) Ordering Code 20 CY7C429–20JC CY7C429–20JXC CY7C429–20PC CY7C429–20VC CY7C429–20DMB 25 CY7C429–25JC CY7C429–25PC CY7C429–25VC CY7C429–25JI CY7C429–25DMB CY7C429–25LMB 30 CY7C429–30JC CY7C429–30PC CY7C429–30VC CY7C429–30DMB 40 CY7C429–40AC CY7C429–40JC CY7C429–40PC 65 CY7C429–65JC CY7C429–65PC CY7C429–65JI Ordering Information (continued) Speed (ns) Ordering Code ...

Page 18

Ordering Information (continued) Speed (ns) Ordering Code 20 CY7C433–20AC CY7C433–20AXC CY7C433–20JC CY7C433–20JXC CY7C433–20PC 25 CY7C433–25JC CY7C433–25PC CY7C433–25VC CY7C433–25JI 30 CY7C433–30JC CY7C433–30PC CY7C433–30JI CY7C433–30PI CY7C433–30DMB CY7C433–30LMB 40 CY7C433–40JC CY7C433–40PC CY7C433–40VC CY7C433–40JI 65 CY7C433–65JC CY7C433–65PC Document #: 38-06001 Rev. *B Package Name ...

Page 19

MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameters Subgroups Max ...

Page 20

Package Diagrams 32-Lead Pb-Free Thin Plastic Quad Flat Pack A32 Document #: 38-06001 Rev. *B 32-Lead Thin Plastic Quad Flat Pack A32 28-Lead (600-Mil) CerDIP D16 MIL-STD-1835 D-10 Config. A CY7C419/21/25/29/33 51-85063-*B 51-80019-** Page [+] Feedback ...

Page 21

Package Diagrams (continued) Document #: 38-06001 Rev. *B 28-Lead (300-Mil) CerDIP D22 MIL-STD-1835 D-15 Config. A CY7C419/21/25/29/33 51-80032-** Page [+] Feedback ...

Page 22

Package Diagrams (continued) 32-Lead Pb-Free Plastic Leaded Chip Carrier J65 32-Pin Rectangular Leadless Chip Carrier L55 Document #: 38-06001 Rev. *B 32-Lead Plastic Leaded Chip Carrier J65 MIL-STD-1835 C-12 CY7C419/21/25/29/33 51-85002-*B 51-80068-** Page [+] Feedback ...

Page 23

Package Diagrams (continued 0.140[3.55] 0.190[4.82] 0.115[2.92] 0.160[4.06] 0.090[2.28] 0.110[2.79] LEAD END OPTION (LEAD #1, 14, 15 & 28) Document #: 38-06001 Rev. *B 28-Lead (600-Mil) Molded DIP P15 28-Lead (300-Mil) PDIP P21 SEE LEAD END OPTION 1 0.260[6.60] ...

Page 24

... Document #: 38-06001 Rev. *B © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

Page 25

... Document History Page Document Title: CY7C419, CY7C421, CY7C425, CY7C429, CY7C433 256/512/1K/2K/4Kx9 Asynchronous FIFO Document Number: 38-06001 Issue Orig. of REV. ECN NO. Date Change ** 106462 07/11/01 SZV *A 122332 12/30/02 RBI *B 383597 See ECN PCX Document #: 38-06001 Rev. *B CY7C419/21/25/29/33 Description of Change Change from Spec Number: 38-00079 to 38-06001 Added power up requirements to maximum ratings information ...

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