CY7C4282V-10ASC Cypress Semiconductor Corp, CY7C4282V-10ASC Datasheet
CY7C4282V-10ASC
Specifications of CY7C4282V-10ASC
Related parts for CY7C4282V-10ASC
CY7C4282V-10ASC Summary of contents
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... Functional Description The CY7C4282V/92V are high-speed, low-power, first-in first- out (FIFO) memories with clocked read and write interfaces. All devices are 9 bits wide. The CY7C4282V/92V can be cas- caded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions ...
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... D 2 Functional Description (continued) The CY7C4282V/92V provides four status pins: Empty, Full, Programmable Almost Empty, and Programmable Almost Full. The Almost Empty/Almost Full flags are programmable to sin- gle word granularity. The programmable flags default to Emp- ty+7 and Full 7. The flags are synchronous, i.e., they change state relative to either the read clock (RCLK) or the write clock (WCLK) ...
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... MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 +150 C Operating Range +125 C Range 0. +0.5V CC Commercial [1] Industrial 0. +0.5V CC Notes: 0. +0. the “instant on” case temperature Range for commercial - 3.3V ± 150 mV CY7C4282V CY7C4292V ; all other devices SS SS Ambient [2] Temperature +70 C 3.3V / 300mV +85 C 3.3V / 300mV ...
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... O CC Com’l Ind Com’l Ind Test Conditions MHz 3.3V CC [6, 7] 3.0V R2=510 GND 3 ns 4282V–4 2.0V /2 3.0V GND CY7C4282V CY7C4292V 7C4282V/92V 7C4282V/92V -15 -25 Min. Max. Min. Max. 2.4 2.4 0.4 0.4 0.4 2 0.8 0.5 0.8 0.5 ...
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... Almost-Empty Flag and Almost-Full Flag Notes: 8. Pulse widths less than minimum values are not allowed. 9. Values guaranteed by design, not currently tested. 7C4282V/92V 7C4282V/92V -10 Min. Max. Min. 100 4.5 6 4 CY7C4282V CY7C4292V 7C4282V/92V -15 -25 Max. Min. Max. Unit 66.7 40 MHz ...
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... REF t A VALID DATA t OE [11] t SKEW1 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 6 CY7C4282V CY7C4292V NO OPERATION t WFF 4282V–6 t REF t OHZ 4282V–7 ...
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... The first word is available the cycle after EF goes HIGH, always. t RSS RSR t RSF t RSF t RSF D 1 [15] t FRL t REF t OLZ When t < minimum specification, t CLK SKEW2 SKEW1 7 CY7C4282V CY7C4292V [14] OE=1 OE [16 (maximum) = either 2 FRL CLK SKEW1 CLK 4282V– 4282V– ...
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... ENS REN LOW –Q DATA IN OUTPUT REGISTER REF REF DATA WRITE t WFF ENH A DATA READ 8 CY7C4282V CY7C4292V DATA WRITE 2 t ENH ENS [15] t FRL t t REF SKEW2 DATA READ 4282V–10 NO WRITE [10] DATA WRITE t SKEW1 t WFF t ENH t ENS t A NEXT DATA READ ...
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... If a read is performed on this rising edge of the read clock, there will be Empty + (n 1) words in the FIFO when PAE goes LOW 20 write is performed on this rising edge of the write clock, there will be Full 21. 64K m words for CY7C4282V, 128K m words for CY4292V. 22 the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK ...
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... PAE OFFSET PAF OFFSET LSB MSB t CLKL t ENH t A UNKNOWN PAE OFFSET LSB t PRT to update these flags. RTR 10 CY7C4282V CY7C4292V PAF OFFSET LSB MSB 4282V–14 PAF OFFSET MSB PAF OFFSET PAE OFFSET MSB LSB 4282V–15 t RTR 4282V–16 . RTR ...
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... Architecture The CY7C4282V/92V consists of an array of 64K to 128K words of 9 bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF , PAE, PAF , FF). Resetting the FIFO Upon power-up, the FIFO must be reset with a Reset (RS) cycle ...
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... PAF is set HIGH by the LOW-to- HIGH transition of WCLK when the number of available mem- ory locations is greater than m. Flag Operation The CY7C4282V/92V devices provide four flag pins to indicate the condition of the FIFO contents. All flags operate synchro- nously. Table 2. Status Flags Number of Words in FIFO ...
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... FF). The partial status flags (PAE and PAF) can be detected from any one device. Figure 2 demonstrates a 18-bit word width by using two CY7C4282V/92V. Any word width can be attained by adding additional CY7C4282V/92V. When the CY7C4282V/92V Width Expansion Configu- ration, the Read Enable (REN) control input can be grounded (see Figure 2) ...
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... Depth Expansion Configuration The CY7C4282V/92V can easily be adapted to applications requiring more than 64K/128K words of buffering. Figure 3 shows Depth Expansion using three CY7C4282V/92Vs. Max- imum depth is limited only by signal loading. Follow these steps: DATA IN (D) WRITECLOCK (WCLK) WRITEENABLE (WEN) RESET (RS) FF FIRST LOAD (FL) Figure 3 ...
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... Ordering Information 64K x 9 Low Voltage Deep Sync FIFO Speed (ns) Ordering Code 10 CY7C4282V-10ASC 15 CY7C4282V-15ASC CY7C4282V-15ASI 25 CY7C4282V-25ASC 128K x 9 Low Voltage Deep Sync FIFO Speed (ns) Ordering Code 10 CY7C4292V-10ASC 15 CY7C4292V-15ASC CY7C4292V-15ASI 25 CY7C4292V-25ASC Document #: 38-00657-B Package Diagram 64-Pin Thin Plastic Quad Flat Pack ( 1.4 mm) A64 © ...