CY7C4292V-15ASC Cypress Semiconductor Corp, CY7C4292V-15ASC Datasheet
CY7C4292V-15ASC
Specifications of CY7C4292V-15ASC
Related parts for CY7C4292V-15ASC
CY7C4292V-15ASC Summary of contents
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... High-speed, low-power, first-in first-out (FIFO) memories • 64K x 9 (CY7C4282V) • 128K x 9 (CY7C4292V) • 0.35 micron CMOS for optimum speed/power • High-speed, Near Zero Latency (True Dual-Ported Memory Cell), 100-MHz operation (10 ns read/write cycle times) • ...
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... CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. 7C4282V/92V-10 7C4282V/92V-15 100 CY7C4282V 64k x 9 64-pin 10x10 TQFP 2 CY7C4282V CY7C4292V GND GND N GND FL/RT N/C 4282V–2 7C4282V/92V-25 66 CY7C4292V 128k x 9 64-pin 10x10 TQFP ...
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... MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 +150 C Operating Range +125 C Range 0. +0.5V CC Commercial [1] Industrial 0. +0.5V CC Notes: 0. +0. the “instant on” case temperature Range for commercial - 3.3V ± 150 mV CY7C4282V CY7C4292V ; all other devices SS SS Ambient [2] Temperature +70 C 3.3V / 300mV +85 C 3.3V / 300mV ...
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... Com’l Ind Com’l Ind Test Conditions MHz 3.3V CC [6, 7] 3.0V R2=510 GND 3 ns 4282V–4 2.0V /2 3.0V GND CY7C4282V CY7C4292V 7C4282V/92V 7C4282V/92V -15 -25 Min. Max. Min. Max. 2.4 2.4 0.4 0.4 0.4 2 0.8 0.5 0.8 0.5 0.8 ...
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... Almost-Empty Flag and Almost-Full Flag Notes: 8. Pulse widths less than minimum values are not allowed. 9. Values guaranteed by design, not currently tested. 7C4282V/92V 7C4282V/92V -10 Min. Max. Min. 100 4.5 6 4 CY7C4282V CY7C4292V 7C4282V/92V -15 -25 Max. Min. Max. Unit 66.7 40 MHz ...
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... REF t A VALID DATA t OE [11] t SKEW1 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 6 CY7C4282V CY7C4292V NO OPERATION t WFF 4282V–6 t REF t OHZ 4282V–7 ...
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... The first word is available the cycle after EF goes HIGH, always. t RSS RSR t RSF t RSF t RSF D 1 [15] t FRL t REF t OLZ When t < minimum specification, t CLK SKEW2 SKEW1 7 CY7C4282V CY7C4292V [14] OE=1 OE [16 (maximum) = either 2 FRL CLK SKEW1 CLK 4282V– 4282V– SKEW1 ...
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... REN LOW –Q DATA IN OUTPUT REGISTER REF REF DATA WRITE t WFF ENH A DATA READ 8 CY7C4282V CY7C4292V DATA WRITE 2 t ENH ENS [15] t FRL t t REF SKEW2 DATA READ 4282V–10 NO WRITE [10] DATA WRITE t SKEW1 t WFF t ENH t ENS t A NEXT DATA READ ...
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... Note t CLKL t t ENS ENH t PAF t ENS (m 1) words of the FIFO when PAF goes LOW. , then PAF may not change state until the next WCLK. 9 CY7C4282V CY7C4292V WORDS 19 Note IN FIFO t PAE t t ENS ENH 4282V–12 FULL M WORDS [21] IN FIFO [22] ...
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... PAE OFFSET PAF OFFSET LSB MSB t CLKL t ENH t A UNKNOWN PAE OFFSET LSB t PRT to update these flags. RTR 10 CY7C4282V CY7C4292V PAF OFFSET LSB MSB 4282V–14 PAF OFFSET MSB PAF OFFSET PAE OFFSET MSB LSB 4282V–15 t RTR 4282V–16 . RTR ...
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... LD WEN Note: 26. The same selection sequence applies to reading from the registers. REN is enabled and a read is performed on the LOW-to-HIGH transition of RCLK. 11 CY7C4282V CY7C4292V 128kx Empty Offset (LSB) Reg. Default Value = 007h 0 8 (MSB) (MSB) Default Value = 000h Default Value = 000h Full Offset (LSB) Reg ...
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... PAF. PAF is synchronized to the LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW when the number of unread words in the FIFO is greater than or equal to CY7C4282V (64K CY7C4292V (128K m). PAF is set HIGH by the LOW-to- HIGH transition of WCLK when the number of available mem- ory locations is greater than m. ...
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... LOW at Reset so that the pin operates as a control to load and read the programmable flag offsets. RESET (RS) 9 7C4282V 7C4292V FIRST LOAD (FL) EXPANSION IN (XI) Configuration 13 CY7C4282V CY7C4292V READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE (OE) PROGRAMMABLE (PAF) EMPTY FLAG (EF) DATA OUT ( 4282V–17 ...
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... EF and FF composite flags are created by ORing together each individual respective flag. XO RCLK WCLK REN WEN OE RS 7C4282V 7C4292V RCLK WCLK REN WEN OE RS 7C4282V D 7C4292V READ CLOCK (RCLK) XO WCLK RCLK READ ENABLE (REN) WEN REN OUTPUTENABLE (OE) RS 7C4282V OE 7C4292V CY7C4282V CY7C4292V DATA OUT (Q) EF 4282V–25 ...
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... Low Voltage Deep Sync FIFO Speed (ns) Ordering Code 10 CY7C4292V-10ASC 15 CY7C4292V-15ASC CY7C4292V-15ASI 25 CY7C4292V-25ASC Document #: 38-00657-B Package Diagram 64-Pin Thin Plastic Quad Flat Pack ( 1.4 mm) A64 © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...