APA600-CQ208B Actel, APA600-CQ208B Datasheet - Page 17

• Manufacturer Part Number: APA600-CQ208B
• Description: FPGA ProASICPLUS Family 600K Gates 180MHz 0.22um (CMOS) Technology 2.5V 208-Pin CQFP
• Manufacturer: Actel

Specifications of APA600-CQ208B

• Package: 208CQFP
• Family Name: ProASICPLUS
• Device System Gates: 600000
• Number Of Registers: 21504
• Maximum Internal Frequency: 180 MHz
• Typical Operating Supply Voltage: 2.5 V
• Maximum Number Of User I/os: 158
• Ram Bits: 129024
• Re-programmability Support: Yes

Power-Up Sequencing
While ProASIC
of V
start-up. V
V
guidelines may result in undesirable pin behavior during
system start-up. For more information, refer to Actel’s
Power-Up Behavior of ProASIC
note.
LVPECL Input Pads
In addition to standard I/O pads and power pads,
ProASIC
both the east and west sides of the device, along with
AVDD and AGND pins to power the PLL block. The
LVPECL pad cell consists of an input buffer (containing a
Figure 2-7 • Recommended Termination for LVPECL Inputs
Figure 2-8 • LVPECL High and Low Threshold Values
Table 2-5 •
Symbol
V
V
V
DDP
IH
IL
ID
DD
on ProASIC
and V
PLUS
DD
LVPECL Receiver Specifications
devices have a single LVPECL input pad on
should be powered up simultaneously with
DDP
PLUS
PLUS
power-up is important during system
devices are live at power-up, the order
From LVPECL Driver
devices. Failure to follow these
Input High Voltage
Input Low Voltage
Differential Input Voltage
NPECL
PPECL
PLUS
Voltage
2.125
Devices
2.72
1.49
0.86
Parameter
Z = 50 Ω
Z = 50 Ω
0
0
application
v5.9
R = 100 Ω
low voltage differential amplifier) and a signal and its
complement, PPECL (I/P) (PECLN) and NPECL (PECLREF).
The LVPECL input pad cell differs from the standard I/O
cell in that it is operated from V
Since it is exclusively an input, it requires no output
signal, output enable signal, or output configuration
bits. As a special high-speed differential input, it also
does not require pull-ups. Recommended termination
for LVPECL inputs is shown in
cell compares voltages on the PPECL (I/P) pad (as
illustrated in
the results to the global MUX
This high-speed, low-skew output essentially controls the
clock conditioning circuit.
LVPECLs are designed to meet LVPECL JEDEC receiver
standard levels
Minimum
1.49
0.86
0.3
Figure
+
_
(Table
2-8) and the NPECL pad and sends
2-5).
Maximum
2.125
ProASIC
2.72
V
DD
Figure
(Figure 2-11 on page
Data
DD
PLUS
only.
2-7. The LVPECL pad
Flash Family FPGAs
Units
V
V
V
2-11).
2-7