APA600-CQ208B Actel, APA600-CQ208B Datasheet - Page 22

• Manufacturer Part Number: APA600-CQ208B
• Description: FPGA ProASICPLUS Family 600K Gates 180MHz 0.22um (CMOS) Technology 2.5V 208-Pin CQFP
• Manufacturer: Actel

Specifications of APA600-CQ208B

• Package: 208CQFP
• Family Name: ProASICPLUS
• Device System Gates: 600000
• Number Of Registers: 21504
• Maximum Internal Frequency: 180 MHz
• Typical Operating Supply Voltage: 2.5 V
• Maximum Number Of User I/os: 158
• Ram Bits: 129024
• Re-programmability Support: Yes

Note: When a signal from an I/O tile is connected to the core, it cannot be connected to the global MUX at the same time.
Figure 2-12 • Input Connectors to ProASIC
Table 2-7 •
2 -1 2
MUX
FBSEL
1
2
3
XDLYSEL
0
1
OBMUX
0
1
2
4
5
6
7
OAMUX
0
1
2
3
ProASIC
PLUS
Clock-Conditioning Circuitry MUX Settings
Flash Family FPGAs
Package Pins
Internal Feedback
Internal Feedback and Advance Clock Using FBDLY
External Feedback (EXTFB)
Feedback Unchanged
Deskew feedback by advancing clock by system delay
Primary bypass, no divider
Primary bypass, use divider
Delay Clock Using FBDLY
Phase Shift Clock by 0°
Reserved
Phase Shift Clock by +180°
Reserved
Secondary bypass, no divider
Secondary bypass, use divider
Delay Clock Using FBDLY
Phase Shift Clock by 0°
NPECL
PPECL
GLMX
GL
GL
Legend
PECL Pad Cell
Physical I/O
Physical Pin
DATA Signals to the Core
DATA Signals to the PLL Block
Std. Pad Cell
Std. Pad Cell
Std. Pad Cell
Buffers
Datapath
PLUS
GLA
GLB
Clock Conditioning Circuitry
CORE
v5.9
DATA Signals to the Global MUX
Control Signals to the Global MUX
Configuration Tile
Configuration Tile
–0.25 to –4 ns in 0.25 ns increments
Fixed delay of –2.95 ns
+0.25 to +4 ns in 0.25 ns increments
+0.25 to +4 ns in 0.25 ns increments
Global MUX
Comments
Global MUX B
OUT
External
Feedback
Global MUX A
OUT