APA600-CQ208B Actel, APA600-CQ208B Datasheet - Page 23

• Manufacturer Part Number: APA600-CQ208B
• Description: FPGA ProASICPLUS Family 600K Gates 180MHz 0.22um (CMOS) Technology 2.5V 208-Pin CQFP
• Manufacturer: Actel

Specifications of APA600-CQ208B

• Package: 208CQFP
• Family Name: ProASICPLUS
• Device System Gates: 600000
• Number Of Registers: 21504
• Maximum Internal Frequency: 180 MHz
• Typical Operating Supply Voltage: 2.5 V
• Maximum Number Of User I/os: 158
• Ram Bits: 129024
• Re-programmability Support: Yes

Table 2-8 •
Lock Signal
An active high Lock signal (added via the SmartGen PLL
development tool) indicates that the PLL has locked to
the incoming clock signal. The PLL will acquire and
maintain a lock even when there is jitter on the incoming
clock signal. The PLL will maintain lock with an input
jitter up to 5% of the input period, with a maximum of
5 ns. Users can employ the Lock signal as a soft reset of
the logic driven by GLB and/or GLA. Note if F
within specified frequencies, then both the F
signal are indeterminate.
PLL Configuration Options
The PLL can be configured during design (via flash-
configuration bits set in the programming bitstream) or
dynamically during device operation, thus eliminating
the need to reprogram the device. The dynamic
configuration bits are loaded into a serial-in/parallel-out
shift register provided in the clock conditioning circuit.
The shift register can be accessed either from user logic
within the device or via the JTAG port. Another option is
internal
hardware. Refer to Actel's
Reconfiguration Using JTAG
information.
For information on the clock conditioning circuit, refer
to Actel’s
application note.
Delay Line
DLYB
0
1
2
3
DLYA
0
1
2
3
Using ProASIC
dynamic
Clock Conditioning Circuitry Delay-Line
Settings
configuration
PLUS
Clock Conditioning Circuits
application note for more
ProASIC
Delay Value (ns)
+0.25
+0.50
+0.25
+0.50
+4.0
+4.0
via
PLUS
0
0
user-designed
PLL Dynamic
OUT
IN
and lock
is not
v5.9
Sample Implementations
Frequency Synthesis
Figure 2-13 on page 2-14
the PLL is used to multiply a 33 MHz external clock up to
133 MHz.
synthesize a 50 MHz output clock from a 40 MHz input
reference clock. The input frequency of 40 MHz is
multiplied by five and divided by four, giving an output
clock (GLB) frequency of 50 MHz. When dividers are
used, a given ratio can be generated in multiple ways,
allowing the user to stay within the operating frequency
ranges of the PLL. For example, in this case the input
divider could have been two and the output divider also
two, giving us a division of the input frequency by four
to go with the feedback loop division (effective
multiplication) by five.
Adjustable Clock Delay
Figure 2-15 on page 2-15
input clock by employing one of the adjustable delay
lines. This is easily done in ProASIC
PLL core entirely and using the output delay line. Notice
also that the output clock can be effectively advanced
relative to the input clock by using the delay line in the
feedback path. This is shown in
Clock Skew Minimization
Figure 2-17 on page 2-16
the clock network can be used to create minimal skew
between the distributed clock network and the input
clock. The input clock is fed to the reference clock input
of the PLL. The output clock (GLA) feeds a clock network.
The feedback input to the PLL uses a clock input delayed
by a routing network. The PLL then adjusts the phase of
the input clock to match the delayed clock, thus
providing nearly zero effective skew between the two
clocks.
Conditioning
information.
Refer
Figure 2-14 on page 2-14
Circuits
to
Actel's
application
ProASIC
indicates how feedback from
illustrates an example where
illustrates the delay of the
Using
Figure 2-16 on page
PLUS
PLUS
uses two dividers to
ProASIC
Flash Family FPGAs
note
by bypassing the
PLUS
for
Clock
more
2-15.
2-13