APA600-CQ208B Actel, APA600-CQ208B Datasheet - Page 33

• Manufacturer Part Number: APA600-CQ208B
• Description: FPGA ProASICPLUS Family 600K Gates 180MHz 0.22um (CMOS) Technology 2.5V 208-Pin CQFP
• Manufacturer: Actel

Specifications of APA600-CQ208B

• Package: 208CQFP
• Family Name: ProASICPLUS
• Device System Gates: 600000
• Number Of Registers: 21504
• Maximum Internal Frequency: 180 MHz
• Typical Operating Supply Voltage: 2.5 V
• Maximum Number Of User I/os: 158
• Ram Bits: 129024
• Re-programmability Support: Yes

Note: Each RAM block contains a multiplexer (called DMUX) for each output signal, increasing design efficiency. These DMUX cells do not
Figure 2-19 • Basic FIFO Block Diagrams
Table 2-15 • Memory Block FIFO Interface Signals
FIFO Signal
WCLKS
RCLKS
LEVEL <0:7>
RBLKB
RDB
RESET
WBLKB
DI<0:8>
WRB
FULL, EMPTY
EQTH, GEQTH
DO<0:8>
RPE
WPE
LGDEP <0:2>
PARODD
consume any core logic tiles and connect directly to high-speed routing resources between the RAM blocks. They are used when
RAM blocks are cascaded and are automatically inserted by the software tools.
LGDEP<0:2>
LEVEL <0:7>
LGDEP<0:2>
LEVEL<0:7>
PARODD
PARODD
DI <0:8>
DI<0:8>
WBLKB
WBLKB
WCLKS
RBLKB
RBLKB
WRB
WRB
RDB
RDB
Bits
1
1
8
1
1
1
1
9
1
2
2
9
1
1
3
1
Async Write
Sync Write
Sync Read
Sync Read
(256x9)
(256x9)
Ports
Ports
FIFO
and
FIFO
and
In/Out
Out
Out
Out
Out
Out
In
In
In
In
In
In
In
In
In
In
In
Write clock used for synchronization on write side
Read clock used for synchronization on read side
Direct configuration implements static flag logic
Read block select (active Low)
Read pulse (active Low)
Reset for FIFO pointers (active Low)
Write block select (active Low)
Input data bits <0:8>, <8> will be generated parity if PARGEN is true
Write pulse (active Low)
FIFO flags. FULL prevents write and EMPTY prevents read
EQTH is true when the FIFO holds the number of words specified by the LEVEL signal.
GEQTH is true when the FIFO holds (LEVEL) words or more
Output data bits <0:8>. <8> will be parity output if PARGEN is true.
Read parity error (active High)
Write parity error (active High)
Configures DEPTH of the FIFO to 2
Parity generation/detect – Even when Low, odd when High
EMPTY
EQTH
RESET
RCLKS
DO <0:8>
EMPTY
EQTH
RESET
DO <0:8>
WPE
RPE
FULL
GEQTH
WPE
RPE
FULL
GEQTH
RCLKS
v5.9
LGDEP<0:2>
LEVEL <0:7>
LGDEP<0:2>
LEVEL<0:7>
PARODD
PARODD
DI <0:8>
DI<0:8>
WBLKB
WBLKB
WCLKS
RBLKB
RBLKB
WRB
WRB
RDB
RDB
(LGDEP+1)
Description
Async Write
Async Read
Async Read
Sync Write
(256x9)
(256x9)
Ports
Ports
FIFO
and
FIFO
and
ProASIC
PLUS
DO <0:8>
RPE
FULL
EMPTY
EQTH
GEQTH
RESET
DO <0:8>
WPE
RPE
FULL
EMPTY
EQTH
GEQTH
RESET
WPE
Flash Family FPGAs
2-23