APA600-CQ208B Actel, APA600-CQ208B Datasheet - Page 53

• Manufacturer Part Number: APA600-CQ208B
• Description: FPGA ProASICPLUS Family 600K Gates 180MHz 0.22um (CMOS) Technology 2.5V 208-Pin CQFP
• Manufacturer: Actel

Specifications of APA600-CQ208B

• Package: 208CQFP
• Family Name: ProASICPLUS
• Device System Gates: 600000
• Number Of Registers: 21504
• Maximum Internal Frequency: 180 MHz
• Typical Operating Supply Voltage: 2.5 V
• Maximum Number Of User I/os: 158
• Ram Bits: 129024
• Re-programmability Support: Yes

Table 2-29 • Worst-Case Military Conditions
Table 2-30 • Worst-Case Military Conditions
Macro Type
OTB33PH
OTB33PN
OTB33PL
OTB33LH
OTB33LN
OTB33LL
Notes:
1. t
2. t
3. t
4. t
Macro Type
OTB25LPHH
OTB25LPHN
OTB25LPHL
OTB25LPLH
OTB25LPLN
OTB25LPLL
Notes:
1. t
2. t
3. t
4. t
5. Low power I/O work with V
DLH
DHL
ENZH
ENZL
DLH
DHL
ENZH
ENZL
= Data-to-Pad High
= Data-to-Pad High
= Data-to-Pad Low
= Data-to-Pad Low
= Enable-to-Pad, Z to Low
= Enable-to-Pad, Z to Low
= Enable-to-Pad, Z to High
= Enable-to-Pad, Z to High
V
V
DDP
DDP
= 3.0 V, V
= 2.3 V, V
3.3 V, Low Output Current, Low Slew Rate
2.5 V, Low Power, High Output Current, Nominal Slew
Rate
2.5 V, Low Power, Low Output Current, High Slew Rate
2.5 V, Low Power, Low Output Current, Low Slew Rate
Description
3.3 V, PCI Output Current, High Slew Rate
3.3 V, High Output Current, Nominal Slew Rate
3.3 V, High Output Current, Low Slew Rate
3.3 V, Low Output Current, High Slew Rate
3.3 V, Low Output Current, Nominal Slew Rate
Description
2.5 V, Low Power, High Output Current, High Slew Rate
2.5 V, Low Power, High Output Current, Low Slew Rate
2.5 V, Low Power, Low Output Current, Nominal Slew Rate
5
DD
DD
DDP
= 2.3 V, 35 pF load, T
= 2.3 V, 35 pF load, T
= 2.5 V ± 10% only. V
J
J
= 125°C for Military/MIL-STD-883
= 125°C for Military/MIL-STD-883
DDP
= 2.3 V for delays.
v5.9
5
5
5
5
5
Max.
t
Max.
t
Std.
Std.
DLH
DLH
2.2
2.4
2.7
2.7
3.3
3.2
2.3
2.7
3.2
3.0
3.7
4.4
1
1
Max.
t
Max.
t
Std.
Std.
DHL
DHL
2.4
3.2
3.5
4.3
4.7
6.0
2.3
3.2
3.5
5.0
4.5
5.8
ProASIC
2
2
t
t
Max.
Max.
ENZH
ENZH
Std.
Std.
PLUS
2.3
2.7
2.9
3.0
3.4
3.5
2.4
2.8
3.3
3.2
4.1
4.4
3
3
Flash Family FPGAs
t
t
Max.
Max.
ENZL
Std.
ENZL
Std.
2.1
2.3
3.0
3.1
4.4
5.9
2.1
2.1
2.8
2.8
4.1
5.4
4
4
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-43