APA600-CQ208B Actel, APA600-CQ208B Datasheet - Page 62

• Manufacturer Part Number: APA600-CQ208B
• Description: FPGA ProASICPLUS Family 600K Gates 180MHz 0.22um (CMOS) Technology 2.5V 208-Pin CQFP
• Manufacturer: Actel

Specifications of APA600-CQ208B

• Package: 208CQFP
• Family Name: ProASICPLUS
• Device System Gates: 600000
• Number Of Registers: 21504
• Maximum Internal Frequency: 180 MHz
• Typical Operating Supply Voltage: 2.5 V
• Maximum Number Of User I/os: 158
• Ram Bits: 129024
• Re-programmability Support: Yes

Table 2-48 • Recommended Operating Conditions
Table 2-49 • Slew Rates Measured at C = 30pF, Nominal Power Supplies and 25°C
2 -5 2
Parameter
Maximum Clock Frequency*
Maximum RAM Frequency*
Maximum Rise/Fall Time on Inputs*
•
•
Maximum LVPECL Frequency*
Maximum TCK Frequency (JTAG)
Type
OB33PH
OB33PN
OB33PL
OB33LH
OB33LN
OB33LL
OB25LPHH
OB25LPHN
OB25LPHL
OB25LPLH
OB25LPLN
OB25LPLL
ProASIC
Schmitt Trigger Mode (10% to 90%)
Non-Schmitt Trigger Mode (10% to
90%)
PLUS
Trig. Level Rising Edge (ns)
10%-90%
10%-90%
10%-90%
10%-90%
10%-90%
10%-90%
10%-90%
10%-90%
10%-90%
10%-90%
10%-90%
10%-90%
Flash Family FPGAs
1.60
1.57
1.57
3.80
4.19
5.49
1.55
1.70
1.97
3.57
4.65
5.52
Symbol
f
CLOCK
f
t
t
f
RAM
R
R
TCK
Slew Rate (V/ns)
/t
/t
F
F
1.65
1.68
1.68
0.70
0.63
0.48
1.29
1.18
1.02
0.56
0.43
0.36
v5.9
Commercial/Industrial
Falling Edge (ns)
180 MHz
150 MHz
180 MHz
10 MHz
100 ns
N/A
1.65
3.32
1.99
4.84
3.37
2.98
1.56
2.08
2.09
3.93
3.28
3.44
Limits
Slew Rate (V/ns)
1.60
0.80
1.32
0.55
0.78
0.89
1.28
0.96
0.96
0.51
0.61
0.58
Military/MIL-STD-883
180 MHz
150 MHz
180 MHz
10 MHz
100 ns
10 ns
PCI Mode
Yes
No
No
No
No
No
No
No
No
No
No
No