APA600-CQ208B Actel, APA600-CQ208B Datasheet - Page 78

• Manufacturer Part Number: APA600-CQ208B
• Description: FPGA ProASICPLUS Family 600K Gates 180MHz 0.22um (CMOS) Technology 2.5V 208-Pin CQFP
• Manufacturer: Actel

Specifications of APA600-CQ208B

• Package: 208CQFP
• Family Name: ProASICPLUS
• Device System Gates: 600000
• Number Of Registers: 21504
• Maximum Internal Frequency: 180 MHz
• Typical Operating Supply Voltage: 2.5 V
• Maximum Number Of User I/os: 158
• Ram Bits: 129024
• Re-programmability Support: Yes

Asynchronous FIFO Write
Note: The plot shows the normal operation status.
Figure 2-41 • Asynchronous FIFO Write
Table 2-64 • T
2 -6 8
Symbol t
DWRH
DWRS
DWRS
EWRH, FWRH,
THWRH
EWRA
FWRA
THWRA
WPDA
WPDH
WRCYC
WRRDS
WRH
WRL
Notes:
1. At fast cycles, EWRA, FWRA = MAX (7.5 ns – WRL), 3.0 ns.
2. At fast cycles, WRRDS (for enabling write) = MAX (7.5 ns – RDL), 3.0 ns.
3. After FIFO reset, WRB needs an initial falling edge prior to any write actions.
ProASIC
PLUS
xxx
T
J
J
Flash Family FPGAs
= 0°C to 110°C; V
= –55°C to 150°C, V
DI setup to WB ↑
DI setup to WB ↑
Old EMPTY, FULL, EQTH, & GETH valid hold
time after WB ↑
WB ↓
DI hold from WB ↑
EMPTY ↓ access from WB ↑
New FULL access from WB ↑
EQTH or GETH access from WB ↑
WPE access from DI
WPE hold from DI
Cycle time
RB ↑, clearing FULL, setup to
WB high phase
WB low phase
WB = (WRB + WBLKB)
Description
DD
DD
= 2.3 V to 2.7 V for Commercial/Industrial
EQTH, GETH
= 2.3 V to 2.7 V for Military/MIL-STD-883
WDATA
EMPTY
t WRRDS
FULL
WPE
RB
t WPDA
t EWRH , t FWRH
t EWRA , t FWRA
t DWRS
Cycle Start
t WRL
Min.
3.0
3.0
3.0
1.5
0.5
2.5
4.5
3.0
7.5
3.0
3.0
v5.9
1
1
2
t WRCYC
Max.
0.5
1.0
1.0
t THWRH
t THWRA
t WRH
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Full inhibits write)
t DWRH
t WPDH
PARGEN is inactive
PARGEN is active
Empty/full/thresh are invalid from the end
of hold until the new access is complete
WPE is invalid while PARGEN is active
Enabling the write operation
Inhibiting the write operation
Inactive
Active
Notes