APA600-CQ208B Actel, APA600-CQ208B Datasheet - Page 80

• Manufacturer Part Number: APA600-CQ208B
• Description: FPGA ProASICPLUS Family 600K Gates 180MHz 0.22um (CMOS) Technology 2.5V 208-Pin CQFP
• Manufacturer: Actel

Specifications of APA600-CQ208B

• Package: 208CQFP
• Family Name: ProASICPLUS
• Device System Gates: 600000
• Number Of Registers: 21504
• Maximum Internal Frequency: 180 MHz
• Typical Operating Supply Voltage: 2.5 V
• Maximum Number Of User I/os: 158
• Ram Bits: 129024
• Re-programmability Support: Yes

Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)
Note: The plot shows the normal operation status.
Figure 2-43 • Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)
Table 2-66 • T
2 -7 0
Symbol t
CCYC
CMH
CML
ECBA
FCBA
ECBH, FCBH,
THCBH
OCA
OCH
RDCH
RDCS
RPCA
RPCH
HCBA
Note: *At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMS), 3.0 ns.
ProASIC
PLUS
xxx
T
J
J
Flash Family FPGAs
= 0°C to 110°C; V
= –55°C to 150°C, V
Cycle time
Clock high phase
Clock low phase
New EMPTY access from RCLKS ↓
FULL ↓ access from RCLKS ↓
Old EMPTY, FULL, EQTH, & GETH valid hold
time from RCLKS ↓
New DO access from RCLKS ↑
Old DO valid from RCLKS ↑
RDB hold from RCLKS ↑
RDB setup to RCLKS ↑
New RPE access from RCLKS ↑
Old RPE valid from RCLKS ↑
EQTH or GETH access from RCLKS ↓
EQTH, GETH
Description
DD
RDATA
EMPTY
RCLK
FULL
DD
RDB
RPE
= 2.3 V to 2.7 V for Commercial/Industrial
t RDCS
= 2.3 V to 2.7 V for Military/MIL-STD-883
t RDCH
t ECBH , t FCBH
Cycle Start
t CMH
Min.
3.0*
3.0*
v5.9
Old Data Out
t CCYC
7.5
3.0
3.0
2.0
0.5
1.0
4.0
4.5
Old RPE Out
t THCBH
t HCBA
Max.
0.75
t CML
1.0
1.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t RPCA
New Valid Data Out
Empty/full/thresh are invalid from the end of
hold until the new access is complete
New RPE Out
t OCA
t ECBA , t FCBA
t RPCH
t OCH
Notes