72821L25TF Integrated Device Technology (Idt), 72821L25TF Datasheet

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72821L25TF

Manufacturer Part Number
72821L25TF
Description
FIFO Mem Sync Quad Depth/Width Bi-Dir 1K x 9 x 2 64-Pin STQFP
Manufacturer
Integrated Device Technology (Idt)
Datasheet

Specifications of 72821L25TF

Package
64STQFP
Configuration
Quad
Bus Directional
Bi-Directional
Density
18 Kb
Organization
1Kx9x2
Data Bus Width
9 Bit
Timing Type
Synchronous
Expansion Type
Depth|Width
Typical Operating Supply Voltage
5 V
Operating Temperature
0 to 70 °C
©2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FEATURES:
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DESCRIPTION:
(clocked) FIFOs. The device is functionally equivalent to two IDT72201/72211/
72221/72231/72241/72251 FIFOs in a single package with all associated
control, data, and flag lines assigned to separate pins.
FUNCTIONAL BLOCK DIAGRAM
IDT, IDT logo and the
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
The IDT72801 is equivalent to two IDT72201 256 x 9 FIFOs
The IDT72811 is equivalent to two IDT72211 512 x 9 FIFOs
The IDT72821 is equivalent to two IDT72221 1,024 x 9 FIFOs
The IDT72831 is equivalent to two IDT72231 2,048 x 9 FIFOs
The IDT72841 is equivalent to two IDT72241 4,096 x 9 FIFOs
The IDT72851 is equivalent to two IDT72251 8,192 x 9 FIFOs
Offers optimal combination of large capacity, high speed,
design flexibility and small footprint
Ideal for prioritization, bidirectional, and width expansion
applications
10 ns read/write cycle time for the IDT72801/72811/72821/72831/
72841/72851
Separate control lines and data lines for each FIFO
Separate Empty, Full, Programmable Almost-Empty and Almost-
Full flags for each FIFO
Enable puts output data lines in high-impedance state
Space-saving 64-pin Thin Quad Flat Pack (TQFP) and Slim Thin
Quad Flatpack (STQFP)
Green parts available, see ordering information
WRITE CONTROL
WCLKA
WRITE POINTER
The IDT72801/72811/72821/72831/72841/72851 are dual synchronous
Industrial temperature range (–40° ° ° ° ° C to +85° ° ° ° ° C) is available
RESET LOGIC
LOGIC
WENA1
RSA
WENA2
SyncFIFO
OEA
logo are registered trademarks of Integrated Device Technology, Inc.
OUTPUT REGISTER
INPUT REGISTER
1024 x 9, 2048 x 9,
4096 x 9, 8192 x 9
256 x 9, 512 x 9,
RAM ARRAY
QA0 - QA8
DA0 - DA8
DUAL CMOS SyncFIFO™
DUAL 256 x 9, DUAL 512 x 9,
DUAL 1,024 x 9, DUAL 2,048 x 9,
DUAL 4,096 x 9, DUAL 8,192 x 9
OFFSET REGISTER
READ CONTROL
READ POINTER
RCLKA
LOGIC
LOGIC
RENA1
FLAG
RENA2
LDA
EFA
PAEA
PAFA
FFA
1
IDT72801/72811/72821/72831/72841/72851 has a 9-bit input data port (DA0
- DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8, QB0 - QB8). Each
input port is controlled by a free-running clock (WCLKA, WCLKB), and two Write
Enable pins (WENA1, WENA2, WENB1, WENB2). Data is written into each of
the two arrays on every rising clock edge of the Write Clock (WCLKA, WCLKB)
when the appropriate write enable pins are asserted.
(RCLKA, RCLKB) and two Read Enable pins (RENA1, RENA2, RENB1,
RENB2). The Read Clock can be tied to the Write Clock for single clock operation
or the two clocks can run asynchronous of one another for dual clock operation.
An Output Enable pin (OEA, OEB) is provided on the read port of each FIFO
for three-state output control.
FFB). Two programmable flags, Almost-Empty (PAEA, PAEB) and Almost-Full
(PAFA, PAFB), are provided for each FIFO bank to improve memory utilization.
If not programmed, the programmable flags default to empty+7 for PAEA and
PAEB, and full-7 for PAFA and PAFB.
to many flexible configurations such as:
CMOS technology.
WRITE CONTROL
WRITE POINTER
• 2-level priority data buffering
• Bidirectional operation
• Width expansion
• Depth expansion
WCLKB
RESET LOGIC
Each of the two FIFOs (designated FIFO A and FIFO B) contained in the
The output port of each FIFO bank is controlled by its associated clock pin
Each of the two FIFOs has two fixed flags, Empty (EFA, EFB) and Full (FFA,
The IDT72801/72811/72821/72831/72841/72851 architecture lends itself
These FIFOs is fabricated using IDT's high-performance submicron
WENB1
LOGIC
RSB
WENB2
OEB
OUTPUT REGISTER
INPUT REGISTER
1024 x 9, 2048 x 9,
4096 x 9, 8192 x 9
256 x 9, 512 x 9,
RAM ARRAY
DB0 - DB8
QB0 - QB8
JANUARY 2009
OFFSET REGISTER
READ POINTER
READ CONTROL
RCLKB
LOGIC
LOGIC
RENB1
FLAG
RENB2
LDB
IDT72801
IDT72811
IDT72821
IDT72831
IDT72841
IDT72851
DSC-3034/5
3034 drw 01
EFB
PAEB
PAFB
FFB

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72821L25TF Summary of contents

Page 1

FEATURES: • • • • • The IDT72801 is equivalent to two IDT72201 256 x 9 FIFOs • • • • • The IDT72811 is equivalent to two IDT72211 512 x 9 FIFOs • • • • • The IDT72821 ...

Page 2

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL PIN CONFIGURATION ...

Page 3

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL PIN DESCRIPTIONS The IDT72801/72811/72821/72831/72841/72851s two FIFOs, referred to as FIFO A and ...

Page 4

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL ABSOLUTE MAXIMUM RATINGS Symbol Rating Terminal Voltage with V TERM Respect to ...

Page 5

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL ELECTRICAL CHARACTERISTICS (Commercial ± 10 0°C ...

Page 6

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL SIGNAL DESCRIPTIONS FIFO A and FIFO B are identical in every respect. ...

Page 7

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL LDA LDA LDA LDA LDA WENA1 WENA1 WENA1 WENA1 WENA1 WCLKA OPERATION ...

Page 8

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL Programmable Almost–Full Flag (PAFA, PAFB) — PAFA (PAFB) will go LOW when ...

Page 9

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL RSA (RSB) RENA1, RENA2 (RENB1, RENB2) WENA1 (WENB1) (1) WENA2/LDA (WENB2/LDB) EFA, ...

Page 10

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL RCLKA (RCLKB) t ENS RENA1, RENA2 (RENB1, RENB2) EFA (EFB ...

Page 11

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL WRITE WCLKA (WCLKB) t SKEW1 (DB ...

Page 12

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL CLKH WCLKA (WCLKB) WENA1 (WENB1) WENA2 (WENB2) (If Applicable) PAFA (PAFB) ...

Page 13

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL CLK WCLKA (WCLKB) LDA (LDB) t WENA1 (WENB1 ...

Page 14

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION — When FIFO A ( ...

Page 15

IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL TWO PRIORITY DATA BUFFER CONFIGURATION The two FIFOs contained in the IDT72801/72811/72821/72831/72841/ ...

Page 16

DEPTH EXPANSION — IDT72801/72811/72821/72831/72841/72851 can be adapted to applications that require greater than 256/512/1,024/ 2,048/4,096/8,192 words. The existence of double enable pins on the read and write ports allow depth expansion. The Write Enable 2/Load (WENA2, WENB2) pins are used ...

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