HY27US08281A-TPCB Hynix, HY27US08281A-TPCB Datasheet
HY27US08281A-TPCB
Specifications of HY27US08281A-TPCB
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HY27US08281A-TPCB Summary of contents
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Document Title 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash Memory Revision History Revision No. 0.0 Initial Draft. 1) Correct Summary description & page.7 - The Cache feature is deleted in summary description. - Note.3 is deleted. (page.7) 2) Correct table.5 & ...
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Revision History Revision No. 1) Change AC Characteristics (1.8V device) tRC tRP Before 50 25 After Change AC Parameter Before 0.3 After 3) Add Read ID Table 4) Edit Automatic Read at Power On & Power On/Off ...
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... VCC = 2.7 to 3.6V Memory Cell Array = (512+16) Bytes x 32 Pages x 1,024 Blocks = (256+8) Words x 32 pages x 1,024 Blocks PAGE SIZE - x8 device : (512 + 16 spare) Bytes : HY27US08281A - x16 device: (256 + 8 spare) Words : HY27US16281A BLOCK SIZE - x8 device: (16K + 512 spare) Bytes - x16 device: (8K + 256 spare) Words PAGE READ / PROGRAM - Random access: 10us (max ...
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... This device includes also extra features like OTP/Unique ID area, Block Lock mechanism, Automatic Read at Power Up, Read ID2 extension. The Hynix HY27US(08/16)281A series is available TSOP1 mm USOP1 mm. 1.1 Product List PART NUMBER HY27US08281A HY27US16281A Rev 0.6 / Nov. 2005 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash ORIZATION ...
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IO15 - IO8 IO7 - IO0 CLE ALE CE# RE# WE# WP# RB# Vcc Vss NC PRE Rev 0.6 / Nov. 2005 HY27US(08/16)281A Series 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash Figure1: Logic Diagram Data Input / Outputs (x16 Only) Data ...
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Figure 2. 48TSOP1 Contactions, x8 and x16 Device Figure 3. 48USOP1 Contactions, x8 and x16 Device Rev 0.6 / Nov. 2005 HY27US(08/16)281A Series 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash 6 ...
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PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS IO0-IO7 The IO pins allow to input command, address and data and to output data during read / program IO8-IO15(1) operations. The inputs are latched on the rising edge of Write Enable (WE#). ...
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IO0 1st Cycle A0 2nd Cycle A9 3rd Cycle A17 NOTE must be set to Low set to LOW or High by the 00h or 01h Command. IO0 1st Cycle A0 2nd Cycle A9 3rd ...
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CLE ALE CE ( NOTE: 1. With ...
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BUS OPERATION There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than Chip Enable, Write Enable and Read ...
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DEVICE OPERATION 3.1 Page Read. Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with followed by the three address input cycles. Once the ...
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Block Erase. The Erase operation is done on a block (16K Byte) basis. It consists of an Erase Setup command (60h), a Block address loading and an Erase Confirm Command (D0h). The Erase Confirm command (D0h) following the block ...
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Read Status Register. The device contains a Status Register which may be read to find out whether read, program or erase operation is com- pleted, and whether the program or erase operation is completed successfully. After writing 70h command ...
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OTHER FEATURES 4.1 Data Protection & Power On/Off Sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2.0V (3.3V device). WP# pin ...
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Unlock - Command Sequence: Unlock block Command (23h) + Start block address + Command (24h) + End block address. See Fig. 19. - Unlocked blocks can be programmed or erased unlocked block’s status can be changed to ...
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Parameter Symbol Valid Block Number Symbol Ambient Operating Temperature (Commercial Temperature Range) T Ambient Operating Temperature (Extended Temperature Range) A Ambient Operating Temperature (Industrial Temperature Range) T Temperature Under Bias BIAS T Storage Temperature STG (2) Input or Output Voltage ...
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Rev 0.6 / Nov. 2005 HY27US(08/16)281A Series 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash Figure 4: Block Diagram 17 ...
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Parameter Sequential Read Operating Current Program Erase Stand-by Current (TTL) Stand-by Current (CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Level Output Low Voltage Level Output Low Current (RB#) Table 8: DC ...
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Item Input / Output Capacitance Input Capacitance Table 10: Pin Capacitance (TA=25C, F=1.0MHz) Parameter Program Time Dummy Busy Time for the Lock or Lock-tight Block Number of partial Program Cycles in the same page Block Erase Time Table 11: Program ...
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Parameter CLE Setup time CLE Hold time CE# setup time CE# hold time WE# pulse width ALE setup time ALE hold time Data setup time Data hold time Write Cycle time WE# High hold time Data Transfer from Cell to ...
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... Pagae IO Program 0 Pass / Fail Ready/Busy 6 Ready/Busy 7 Write Protect DEVICE IDENTIFIER BYTE 1st 2nd Part Number HY27US08281A HY27US16281A Rev 0.6 / Nov. 2005 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash Block Read Erase Pass / Fail Ready/Busy Ready/Busy Ready/Busy Ready/Busy Write Protect Write Protect Table 13: Status Register Coding ...
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Rev 0.6 / Nov. 2005 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash Table 16: Lock Status Code Figure 5: Command Latch Cycle HY27US(08/16)281A Series 22 ...
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Rev 0.6 / Nov. 2005 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash Figure 6: Address Latch Cycle HY27US(08/16)281A Series 23 ...
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CE RE I/Ox R/B Notes : Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. Figure 8: Sequential Out Cycle after Read (CLE=L, WE#=H, ALE=L) Rev 0.6 / Nov. 2005 128Mbit ...
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Figure 10: Read1 Operation (Read One Page) Rev 0.6 / Nov. 2005 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash Figure 9: Status Read Cycle HY27US(08/16)281A Series 25 ...
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Figure 11: Read1 Operation intercepted by CE# Figure 12: Read2 Operation (Read One Page) Rev 0.6 / Nov. 2005 HY27US(08/16)281A Series 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash 26 ...
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Figure 13: Sequential Row Read Operation Within a Block Rev 0.6 / Nov. 2005 HY27US(08/16)281A Series 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash 27 ...
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Rev 0.6 / Nov. 2005 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash Figure 14: Page Program Operation HY27US(08/16)281A Series 28 ...
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Rev 0.6 / Nov. 2005 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash Figure 15 : Copy Back Program HY27US(08/16)281A Series 29 ...
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Figure 16: Block Erase Operation (Erase One Block) Rev 0.6 / Nov. 2005 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash Figure 17: Read ID Operation HY27US(08/16)281A Series 30 ...
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Rev 0.6 / Nov. 2005 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash Figure 18: Lock Command Figure 19: Unlock Command Sequence HY27US(08/16)281A Series 31 ...
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Rev 0.6 / Nov. 2005 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash Figure 20: Lock Tight Command Figure 21: Lock Status Read Timing HY27US(08/16)281A Series 32 ...
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Rev 0.6 / Nov. 2005 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash Figure 22: Automatic Read at Power On Figure 23: Reset Operation HY27US(08/16)281A Series 33 ...
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Rev 0.6 / Nov. 2005 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash Figure 24: Power On/Off Timing V = 2.5 Volt for 3.3 Volt Supply devices TH HY27US(08/16)281A Series 34 ...
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Figure 25: Ready/Busy Pin electrical specifications Rev 0.6 / Nov. 2005 HY27US(08/16)281A Series 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash 35 ...
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Rev 0.6 / Nov. 2005 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash Figure 26: Lock/Unlock FSM Flow Cart Figure 27: Pointer operations HY27US(08/16)281A Series 36 ...
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Figure 28: Pointer Operations for porgramming Rev 0.6 / Nov. 2005 HY27US(08/16)281A Series 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash 37 ...
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System Interface Using CE don’t care To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below. So possible to connect NAND Flash to a microprocessor. The only function that was removed ...
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Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it ...
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Write Protect Operation The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 32~35) Rev 0.6 / Nov. 2005 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash ...
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Rev 0.6 / Nov. 2005 HY27US(08/16)281A Series 128Mbit (16Mx8bit / 8Mx16bit) NAND Flash Figure 34: Enable Erasing Figure 35: Disable Erasing 41 ...
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Figure 36: 48pin-TSOP1 20mm, Package Outline Symbol alpha Table 18: 48pin-TSOP1 20mm, Package Mechanical Data Rev 0.6 / Nov. 2005 128Mbit (16Mx8bit / 8Mx16bit) NAND ...
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Figure 37. 48pin-USOP1 17mm, Package Outline Symbol alpha Table 19: 48pin-USOP1 17mm, Package Mechanical Data Rev 0.6 / Nov. 2005 HY27US(08/16)281A Series 128Mbit (16Mx8bit / ...
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MARKING INFORMATION - ...