PALCE22V10Z-25SC Lattice, PALCE22V10Z-25SC Datasheet

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PALCE22V10Z-25SC

Manufacturer Part Number
PALCE22V10Z-25SC
Description
SPLD PAL® Family 10 Macro Cells 50MHz EECMOS Technology 5V 24-Pin SOIC
Manufacturer
Lattice
Datasheet

Specifications of PALCE22V10Z-25SC

Package
24SOIC
Family Name
PAL®
Number Of Macro Cells
10
Maximum Propagation Delay Time
25 ns
Typical Operating Supply Voltage
5 V
Maximum Internal Frequency
50 MHz
Number Of Product Terms Per Macro
16
Re-programmability Support
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PALCE22V10Z-25SC
Manufacturer:
AMD
Quantity:
20 000
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The PALCE22V10 provides user-programmable logic for replacing conventional SSI/MSI gates and
flip-flops at a reduced chip count.
The PALCE22V10Z is an advanced PAL
erasable CMOS technology. It provides user-programmable logic for replacing conventional zero-
power CMOS SSI/MSI gates and flip-flops at a reduced chip count.
The PALCE22V10Z provides zero standby power and high speed. At 30 µA maximum standby
current, the PALCE22V10Z allows battery-powered operation for an extended period.
The PAL device implements the familiar Boolean logic transfer function, the sum of products. The
PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed
to create custom product terms, while the OR array sums selected terms at the outputs.
The product terms are connected to the fixed OR array with a varied distribution from 8 to16 across
the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each
macrocell can be programmed as registered or combinatorial, and active-high or active low. The
output configuration is determined by two bits controlling two multiplexers in each macrocell.
Publication# 16564
Amendment/0
As fast as 5-ns propagation delay and 142.8 MHz f
Low-power EE CMOS
10 macrocells programmable as registered or combinatorial, and active high or active low to
match application needs
Varied product term distribution allows up to 16 product terms per output for complex
functions
Peripheral Component Interconnect (PCI) compliant (-5/-7/-10)
Global asynchronous reset and synchronous preset for initialization
Power-up reset for initialization and register preload for testability
Extensive third-party software and programmer support
24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC
5-ns and 7.5-ns versions utilize split leadframes for improved performance
Rev: E
Issue Date: November 1998
PALCE22V10 and PALCE22V10Z
Families
24-Pin EE CMOS (Zero Power) Versatile PAL Device
PALCE22V10
PALCE22V10Z
®
device built with zero-power, high-speed, electrically-
COM'L: H-5/7/10/15/25,Q-10/15/25 IND: H-10/15/20/25
COM'L: -25
MAX
(external)
IND: -15/25

Related parts for PALCE22V10Z-25SC

PALCE22V10Z-25SC Summary of contents

Page 1

... CMOS technology. It provides user-programmable logic for replacing conventional zero- power CMOS SSI/MSI gates and flip-flops at a reduced chip count. The PALCE22V10Z provides zero standby power and high speed µA maximum standby current, the PALCE22V10Z allows battery-powered operation for an extended period. ...

Page 2

... PC board and placed on silicon, where they can be easily modified during prototyping or production. The PALCE22V10Z is the zero-power version of the PALCE22V10. It has all the architectural features of the PALCE22V10. In addition, the PALCE22V10Z has zero standby power and unused product term disable. ...

Page 3

... In the combinatorial configuration, the feedback is from the pin GND I Programmed EE bit 1 = Erased (charged) EE bit Figure 1. Output Logic Macrocell Diagram PALCE22V10 and PALCE22V10Z Families S Output Configuration 0 0 Registered/Active Low 1 Registered/Active High 0 Combinatorial/Active Low 1 Combinatorial/Active High 16564E-004 3 ...

Page 4

... HIGH on the next LOW-to-HIGH clock transition. When the asynchronous reset (AR) product term is asserted high, the output registers will be immediately loaded with a LOW independent of the clock Combinatorial/active low d. Combinatorial/active high in the output macrocell, and affects both registered 0 = 1). 0 PALCE22V10 and PALCE22V10Z Families 16564E-005 ...

Page 5

... PCI AC specifications independent of the design. Zero-Standby Power Mode The PALCE22V10Z features a zero-standby power mode. When none of the inputs switch for an extended period (typically 50 ns), the PALCE22V10Z will go into standby mode, shutting down PALCE22V10 and PALCE22V10Z Families ...

Page 6

... This saving is illustrated in the I Product-Term Disable On a programmed PALCE22V10Z, any product terms that are not used are disabled. Power is cut off from these product terms so that they do not draw current. As shown in the I graph, product-term disabling results in considerable power savings. This saving is greater at the higher frequencies ...

Page 7

... LOGIC DIAGRAM CLK ( ( ( ( ( ( (9) 98 110 (10) 111 121 (11) 122 130 (12) 131 (13 GND 12 (14 PALCE22V10 and PALCE22V10Z Families 24 (28 I (27 I (26 I (25 I (24 I (23 I (21 I (20 I (19 I (18 I (17 (16) 43 16564E-006 ...

Page 8

ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65 ° +150 ° C Ambient Temperature with Power Applied . . . . . . . . . . ...

Page 9

CAPACITANCE Parameter Symbol Parameter Description C Input Capacitance IN C Output Capacitance OUT Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

Page 10

ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . . ...

Page 11

CAPACITANCE Parameter Symbol Parameter Description C Input Capacitance IN C Output Capacitance OUT Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

Page 12

ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . . ...

Page 13

CAPACITANCE Parameter Symbol Parameter Description C Input Capacitance IN C Output Capacitance OUT Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

Page 14

ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . . ...

Page 15

CAPACITANCE Parameter Symbol Parameter Description C Input Capacitance IN C Output Capacitance OUT Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

Page 16

ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . . ...

Page 17

CAPACITANCE Parameter Symbol Parameter Description C Input Capacitance IN C Output Capacitance OUT Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

Page 18

ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . . ...

Page 19

CAPACITANCE Parameter Symbol Parameter Description C Input Capacitance IN C Output Capacitance OUT Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

Page 20

... Guaranteed Input Logical LOW Voltage for all Inputs (Notes Max (Note Max (Note 3) V OUT = Max (Note 3) V OUT = Max (Note 3) V OUT = 0 Max (Note MHz Outputs Open (I OUT = 0 mA Max MHz PALCE22V10Z-15 (Ind -40°C to +85° with Min Max Unit 3. -0.1 V ...

Page 21

... 1/f (internal feedback MAX S Test Conditions 2 OUT = 2.0 V Parameter Description 1/( 1/( (Note 3) CNT S CF 1/( can be found using the following equation PALCE22V10Z-15 (Ind) Typ Unit 5 25° MHz 1 -15 Min Max 58 Unit ...

Page 22

... Guaranteed Input Logical LOW Voltage for all Inputs (Notes Max (Note Max (Note 3) V OUT = Max (Note 3) V OUT = Max (Note 3) V OUT = 0 Max (Note MHz Outputs Open (I OUT = 0 mA Max MHz PALCE22V10Z-25 (Com’l, Ind 0°C to +75° with -40°C to +85° with CC Min Max Unit 3 ...

Page 23

... CF MAX S Test Conditions 2 OUT = 2.0 V Parameter Description LOW HIGH External Feedback 1/( Internal Feedback (f ) 1/( (Note CNT No Feedback 1/( can be found using the following equation: CF PALCE22V10Z-25 (Com’l, Ind) Typ Unit 5 25° MHz -25 Min Max Unit 33.3 MHz 35.7 ...

Page 24

... Input rise and fall times typical. 24 Input, I/O, or Feedback Clock Registered Output 16564-007 Input t WL Output 16564-009 d. Input to output disable/enable Input Asserting Synchronous V T Preset V Clock T t ARR Registered V Output T 16564-011 PALCE22V10 and PALCE22V10Z Families 16564-008 b. Registered output 0. 0.5V OL 16564-010 SPR ...

Page 25

... Don’t Care, Changing, Any Change State Permitted Unknown Does Not Center Apply Line is High- Impedance “Off” State Test Point 300 5 pF PALCE22V10 and PALCE22V10Z Families 16564E-013 16564-014 Commercial Measured Output R Value 2 1.5 V All except H-5/7: 390 1.5 V H-5/ 300 0 0 ...

Page 26

... By utilizing 50% of the device, a midpoint is defined for I down to estimate the I requirements for a particular design Frequency (MHz vs. Frequency ., From this midpoint, a designer may scale the I CC PALCE22V10 and PALCE22V10Z Families 22V10H-5 22V10H-7 22V10H-10 22V10H-15 22V10H-25 22V10Q-10 22V10Q- 16564E-015 graphs up or ...

Page 27

... I vs. Frequency Graph for the PALCE22V10Z-15 CC TYPICAL I CHARACTERISTICS FOR THE PALCE22V10Z- 5 25° 120 100 (mA *Percent of product terms used. I vs. Frequency Graph for the PALCE22V10Z- Frequency (MHz Frequency (MHz) PALCE22V10 and PALCE22V10Z Families 100%* 50%* 25 16564E-016 100%* 50%* 25%* ...

Page 28

... INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR SELECTED /4 DEVICES* * Device Rev Letter PALCE22V10H-15 PALCE22V10H-20H H PALCE22V10H-25 PALCE22V10Q-25I I 28 Test Conditions Max Storage Temperature Normal Programming Conditions 100 k ESD Protection Input 100 k Preload Feedback Circuitry Input Output PALCE22V10 and PALCE22V10Z Families Value Unit 10 Years 100 Cycles V CC 16564E-018 ...

Page 29

... INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR /5 VERSION DEVICES V CC > ESD Protection and Clamping V CC Programming Programming Pins only Voltage Detection Typical Input > Provides ESD Protection and Clamping Circuitry Typical Output PALCE22V10 and PALCE22V10Z Families Positive Programming Overshoot Circuitry Filter CC Preload Feedback Input 16564-16 29 ...

Page 30

... INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR PALCE22V10Z ESD Input Protection Transition and Detection Clamping Programming Pins only Programming Voltage Detection Typical Input V CC Provides ESD Protection and Clamping Preload Circuitry Typical Output PALCE22V10 and PALCE22V10Z Families Positive Programming Overshoot Circuitry Filter Feedback Input ...

Page 31

... Parameter Symbol Parameter Description t Power-up Reset Time PR t Input or Feedback Setup Time S t Clock Width LOW Power Registered Active-Low Output Clock V CC Off Figure 3. Power-Up Reset Waveform PALCE22V10 and PALCE22V10Z Families can rise CC Max Unit 1000 ns See Switching Characteristics V CC 16564E-021 31 ...

Page 32

... Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant tem- perature. Therefore, the measurements can only be used in a similar environment. 32 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air PALCE22V10 and PALCE22V10Z Families Typ SKINNY DIP PLCC Unit 20 18 ° ...

Page 33

... If not grounded, AC timing may degrade by about 10%. Note: Pin 1 is marked for orientation. PIN DESIGNATIONS CLK = Clock GND = Ground I = Input I/O = Input/Output Connect V = Supply Voltage 16564E-002 PALCE22V10 and PALCE22V10Z Families PLCC GND I/O 2 16564E-003 33 ...

Page 34

... Valid Combinations list configurations planned supported in volume for this device. Consult the local Lattice/Vantis sales office to confirm availability of /4 specific valid combinations and to check on newly released combinations. PALCE22V10 and PALCE22V10Z Families PROGRAMMING DESIGNATOR Blank = Initial Algorithm /4 = First Revision /5 = Second Revision ...

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