ST52T440F3M6 STMicroelectronics, ST52T440F3M6 Datasheet
ST52T440F3M6
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ST52T400/T440/E440 ® 8-BIT INTELLIGENT CONTROLLER UNIT (ICU) Timer/PWM, Analog Comparator, Triac/PWM Timer, WDG Memories Kbytes EPROM/OTP 128/256 bytes of RAM Readout Protection Core Register File Based Architecture 55 instructions Hardware multiplication and division Decision Processor for the ...
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ST52T400/T440/E440/T441 ST52T400/T440/E440/T441 Type List NVM RAM ST52 Device (bytes) (bytes) ST52T400Fmpy 1/2/4/8K 128/256 ST52T400Gmpy 1/2/4/8K 128/256 ST52T440Fmpy 1/2/4/8K 128/256 ST52T440Gmpy 1/2/4/8K 128/256 ST52E440F3D6 8K 256 ST52E440G3D6 8K 256 ST52T441Fmpy 1/2/4/8K 128/256 ST52T441Gmpy 1/2/4/8K 128/256 ST52E441F3D6 8K 256 ST52E441G3D6 8K 256 ...
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TABLE OF CONTENTS 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST52T400/T440/E440/T441 4.5 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Recommended Operating Condition ...
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ST52T400/T440/E440/T441 6/94 ...
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GENERAL DESCRIPTION 1.1 Introduction ST52x400/440/441 are 8-bit Intelligent Control Units (ICU) of the ST Five Family, which are able to perform both boolean and fuzzy algorithms in an efficient manner, in order to reach the best per- formances that ...
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ST52T400/T440/E440/T441 1.2 Operational Description ST52x400/440/441 ICU can work in two modes: Memory Programming Phase Working Phase according to RESET and Vpp signals levels (see pins description) . Note: When RESET advisable not to use the sequence “101010“ to ...
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Figure 1.1 ST52x400/440/441 Block Diagram I/O PORT ANALOG COMPARATOR USER PROGRAM EPROM 8 KBytes CONTROL INT UNIT PC CU Input Registers POWER SUPPLY and BOD VDD VPP ( * ) ...
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ST52T400/T440/E440/T441 Figure 1.2 ST52x400 SO28 Pin Configuration OSCOUT OSCIN Figure 1.3 ST52x400 PDIP28 Pin Configuration OSCOUT OSCIN Vpp PC4 PC3 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Vss 10/94 Vdd 1 28 Vss 2 27 Vpp RESET 3 26 ...
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Figure 1.4 ST52x400 SO20 Pin Configuration Figure 1.5 ST52x400 PDIP20 Pin Configuration ST52T400/T440/E440/T441 11/94 ...
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ST52T400/T440/E440/T441 Figure 1.6 ST52x440/441 SO28 Pin Configuration OSCOUT OSCIN PB7/CS PB6/BG PB5/AC5 PB4/AC4 PB3/AC3 PB2/AC2 PB1/AC1 PB0/AC0 GNDA Figure 1.7 ST52x440/441 PDIP28 Pin Configuration OSCOUT OSCIN PB7/CS PB6/BG PB5/AC5 PB4/AC4 PB3/AC3 PB2/AC2 PB1/AC1 PB0/AC0 GNDA 12/ ...
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Figure 1.8 ST52x440/441 SO20 Pin Configuration Figure 1.9 ST52x440/441 PDIP20 Pin Configuration ST52T400/T440/E440/T441 13/94 ...
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ST52T400/T440/E440/T441 Table 1.2 SO28 and DIP28 Pin Configuration - ST52x400 PIN SO28/DIP28 NAME 1 OSCOUT 2 OSCIN 3 Vpp 4 PC4 5 PC3 6 PB7 7 PB6 8 PB5 9 PB4 10 PB3 11 PB2 12 PB1 13 PB0 14 ...
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Table 1.3 SO20 and DIP20 Pin Configuration - ST52x400 PIN SO20/DIP20 NAME OSCOUT 3 OSCIN 4 Vpp 5 PB7 6 PB3 7 PB2 8 PB1 9 PB0 10 Vss 11 PA0/TROUT 12 PA1/MAIN1 PA2/MAIN2/ 13 TOUTN ...
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ST52T400/T440/E440/T441 Table 1.4 SO28 and DIP28 Pin Configuration - ST52x440/441 PIN SO28/DIP28 NAME 1 OSCOUT 2 OSCIN 3 Vpp 4 PC4 5 PC3 6 PB7/CS 7 PB6/BG 8 PB5/AC5 9 PB4/AC4 10 PB3/AC3 11 PB2/AC2 12 PB1/AC1 13 PB0/AC0 14 ...
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Table 1.5 SO20 and DIP20 Pin Configuration - ST52x440/441 PIN SO20/DIP20 NAME OSCOUT 3 OSCIN 4 Vpp 5 PB7/CS 6 PB3/AC3 7 PB2/AC2 8 PB1/AC1 9 PB0/AC0 10 GNDA 11 PA0/TROUT 12 PA1/MAIN1 PA2/MAIN2/ 13 TOUTN ...
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ST52T400/T440/E440/T441 1.3 Pin Description ST52x400/440/441 pins can be set in digital input mode, digital output mode or in Alternate Func- tions. The pin configuration is achieved by means of the configuration registers. The functions of the ST52x400/440/441 pins are described ...
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INTERNAL ARCHITECTURE ST52x400/440/441 is composed of the following blocks and peripherals: Control Unit (CU) Data Processing Unit (DPU) ALU Decision Processor (DP) EPROM 256 Byte RAM Clock Oscillator Analog Multiplexer and Analog Comparator 1 PWM / Timer 1 Triac/PWM ...
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ST52T400/T440/E440/T441 Figure 2.2 Data Processing Unit (DPU) EPROM INPUTS M PERIPHERALS U X ADDRESS RAM STACK POINT Figure 2.3 CU/DPU Block Diagram 20/94 CU PROGRAM COUNTER add_EPR ...
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The 13-bit length allows the direct addressing of 8192 bytes in the program space: jump and call instruction support the absolute addressing in all the memory. After having read the current instruction address, the PC value is incremented. The result ...
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ST52T400/T440/E440/T441 2.2.1 Ram and Stack. RAM consists of 128 (G0/G1/F0/F1 types) or 256 (G2/G3/F2/F3 types) general purpose 8-bit regis- ters. All the registers in RAM can be specified by using a decimal address, e.g. 0 identifies the first regis- ter ...
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Configuration Registers. The ST52x400/440/441 Configuration Registers allow the configuration of all the blocks of the ICU. Table 2.2 describes the functions and the related peripherals of the 21 Configuration Registers available: in order to simplify the concept a mne- ...
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ST52T400/T440/E440/T441 Table 2.2 Configuration Registers Description CONFIGURATION REGISTER REG_CONF 0 REG_CONF 1(*) REG_CONF 2 REG_CONF 3(*) REG_CONF 4 REG_CONF 5 REG_CONF 6 REG_CONF 7 REG_CONF 8 REG_CONF 9 REG_CONF 10 REG_CONF 11 REG_CONF 12 REG_CONF 13 REG_CONF 14(*) REG_CONF 15(*) ...
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Fuzzy Computation ST FIVE’s Fuzzy main features are Inputs with 8-bit resolution; 1 Kbyte of Program/Data Memory available to store more than 300 to Membership Functions (Mbfs) for each Input 128 Outputs with 8-bit ...
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ST52T400/T440/E440/T441 2.3.3 Inference Phase. The Inference Phase manages the alpha weights obtained during the fuzzyfication phase to com- pute the truth value ( ) for each rule. This is a calculation of the maximum (for the OR operator) and/or minimum ...
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Input Membership Function. ST FIVE allows the management of triangular Mbfs. In order to define an Mbf, three different types of data must be stored on the Program/Data Memory: the vertex of the Mbf: V; the length of the ...
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ST52T400/T440/E440/T441 The assembler Instruction Set, which manages fuzzy instructions is reported in the following table: Table 2.4 Fuzzy Instruction Set Instruction MBF n_mbf Ivd v rvd Stores the Mbf n_mbf with the shape identified by the parameters Ivd , v ...
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Example 1: IF Input IS NOT Mbf AND Input codified by the following instructions: LDN 1 1 calculates the NOT LDP 4 12 fixes the value of Input FZAND adds the NOT and LDK stores the result ...
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ST52T400/T440/E440/T441 2.4 Arithmetic Logic Unit ST52x400/440/441 supplies 46 instructions that perform computations and control the device. Computational time required for each instruction consists of one clock pulse for each Cycle plus 2 clock pulses for the decoding phase. Total compu- ...
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Table 2.6 Arithmetic and Logic Instruction Set (Continued) Mnemonic Instruction ADD ADD regx, regy ADDO ADDO regx, regy AND AND regx, regy ASL ASL regx ASR ASR regx DEC DEC regx DIV DIV regx, regy INC INC regx MULT MULT ...
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ST52T400/T440/E440/T441 Table 2.7 Control Instructions Set Mnemonic Instruction FUZZY FUZZY NOP NOP WDTRFR WDTRFR WDTSLP WDTSLP Notes: | flag affected - flag not affected regx, regy: Register File addresses memx, memy: Program/Data Memory addresses confx, confy: Configuration Registers addresses outx: ...
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EPROM PROGRAMMING EPROM memory provides an on-chip user-pro- grammable non-volatile memory, which allows fast and reliable storage of user data. EPROM memory can be locked by the user. In fact, a memory location, called Lock Cell, is devoted to ...
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ST52T400/T440/E440/T441 The locations 0, 1 and 2 contain the jump instruc- tion to the first code line. This instruction is auto- matically inserted by the Assembler tool. The operations that can be performed on EPROM dur- ing the Programming Phase ...
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INC_ADD (PB1) signal increments the memory address.Control Register. When RST_CONF is high, the DATA I/O Port output, other- wise it is always in input. The signal applied on INC_CONF (PB3) incre- ments the EPROM Control Register value. ...
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ST52T400/T440/E440/T441 3.1.5 Stand by Mode. EPROM has a standby mode which reduces the active current from 10mA (Programming mode) to less than 100 A. Mem- ory is placed in standby mode by setting PHASE signal at high level or when ...
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INTERRUPTS The Control Unit (CU) responds to peripheral events and external events via its interrupt chan- nels. When such an events occur, if the related interrupt is not masked and according to a priority order, the current program execution ...
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ST52T400/T440/E440/T441 4.2 Global Interrupt Request Enabling When an Interrupt occurs, it generates a Global Interrupt Pending (GIP), which can be masked by software. After a GIP, a Global Interrupt Request (GIR) will be generated and an Interrupt Service Routine associated ...
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Table 4.2 Interrupts Description Name INT_AC(*) Analog Comparator INT_PWM/TIMER PWM/TIMER INT_TRIAC/F TRIAC Falling Edge INT_TRIAC/R TRIAC rising edge INT_TRIAC/P TRIAC Pulse INT_EXT External Interrupt (INT) (*) Used only in ST52x440/441 devices Figure 4.4 Interrupt Configuration Register 0 REG_CONF0 Interrupts Mask ...
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ST52T400/T440/E440/T441 Figure 4.5 Interrupt Configuration Registers 17 and 18 REG_CONF18 D15 D14 D13 D12 D11 4.5 Interrupt Priority Seven priority levels are available: level 6 has the lowest priority, level 0 has the highest priority. Level 6 is associated to ...
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Interrupts and Low power mode All interrupts allow the processor to leave WAIT mode. Only an External Interrupt request allows the ...
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ST52T400/T440/E440/T441 5 CLOCK, RESET & POWER SAVING MODE 5.1 Clock System The ST52x400/440/441 Clock Generator module generates the internal clock for the internal Con- trol Unit, ALU and on-chip peripherals and is designed to require a minimum of external compo- ...
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Reset There are four sources of Reset: - RESET pin (external source) - WATCHDOG (internal source) - POWER ON Reset (Internal source) - BROWN OUT Reset (Internal source) When a Reset event happens, all the registers are set to ...
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ST52T400/T440/E440/T441 5.2.4 Brown-Out Detector (BOD). The on-chip Brown-Out Detector circuit prevents the processor from falling into an unpredictable state if the power supply drops below a certain level. When Vdd drops below the Brown-out detection level, the Brown-out causes an ...
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Figure 5.4 HALT Flow Chart HALT INSTRUCTION NO RESET OSCILLATOR PERIPHERALS CLOCK CPU CLOCK 1000000 CPU CLOCK CYCLES DELAY RESET CPU AND RESTART USER PROGRAM HALT INSTRUCTION YES WATCHDOG ENABLED NO SKIPPED OSCILLATOR PERIPHERALS CLOCK CPU CLOCK NO EXTERNAL INTERRUPT ...
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ST52T400/T440/E440/T441 6 I/O PORTS 6.1 Introduction ST52x400/440/441 devices offer flexible individu- ally programmable multi-functional input/output lines. Refer to Chapter 1 for specific pin alloca- tions. 21 I/O lines, grouped in 3 different ports, are avail- able for ST52x400G/440G/441G devices: PORT ...
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Figure 6.2 Port B Functional Blocks FROM CONFIGURATION REGISTER TO INPUT REGISTER FROM OUTPUT REGISTERS FROM CONFIGURATION REGISTER 6.2 Input Mode The input configuration is selected setting the cor- responding configuration REG_CONF4, REG_CONF13 and, where appli- cable, REG_CONF11 (see Paragraph ...
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ST52T400/T440/E440/T441 6.4 Alternate Functions. Port A and B pins in ST52x400/440/441 are con- figurable to be used with different functions (Alter- nate Functions) related to the use of peripherals. To configure a pin in Alternate Function the related configuration registers ...
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Table 6.5 - Port A - REG_CONF 12 Bit Name Value Pin set as Alternate Function Output ...
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ST52T400/T440/E440/T441 7 ANALOG COMPARATOR (ST52X440/441) 7.1 Analog Module Overview The ST52x440/441 includes an Analog Compara- tor (AC) among its peripherals. The Analog Comparator is endowed with analog and digital elements in order to also allow the user to make use ...
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The optimum linearity in conversion can be obtained if the volt- age level on the selected input channel does not exceed a maximum the ...
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ST52T400/T440/E440/T441 The four modes are selected by configuring REG_CONF1[(2)] to choose among the conver- sion of a single channel or a sequence of chan- nels and REG_CONF1[(1)] to conversion once or continuously. REG_CONF1[(5:3)] bits allows the user to choose the ...
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Figure 7.2 Configuration Register 1 REG_CONF 1 Analog Comparator Figure 7.3 Configuration Register 3 Analog Comparator Figure 7.4 Configuration Register 15 REG_CONF 15 Analog ...
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ST52T400/T440/E440/T441 8 WATCHDOG TIMER 8.1 Functional Description The Watchdog Timer (WDT) is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal ...
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Register Description WDT Timeout period can be set by setting the first 4 bits of REG_CONF2: this allows 16 different val- ues of WDT Clock pulse number to be defined. The WDT CLK is derived from the Master Clock ...
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ST52T400/T440/E440/T441 9 PWM/TIMER ST52x400/440/441 on-chip PWM/TIMER periph- erals consist of an 8-bit counter with a 16-bit pro- grammable prescaler that provide a maximum 24 count of 2 (Figure 9.1). The TIMER has two different working modes: Timer Mode PWM (Pulse ...
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Figure 9.2 Timer 0 External START/STOP Mode ...
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ST52T400/T440/E440/T441 Figure 9.4 PWM Mode with Auto Reload 255 compare value reload register 0 PWM Output The 16-bit Prescaler divides the master clock, CLKM or the external signal TCLK. The Prescaler output can be selected setting the PRESC bit of ...
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Timer Interrupt The TIMER can be programmed to generate an Interrupt request until the end of the count or when there is an Timer Stop signal (TSTRT). The Timer can generate programmable Interrupts into 4 dif- ferent modes: Interrupt ...
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ST52T400/T440/E440/T441 Figure 9.5 Configuration Register 5 REG_CONF 5 TIMER Reset Configuration = “00000000” 60/94 TIRST: Timer Internal RESET TERST: Timer External RESET on Edge/Level TISTR: Timer Internal START TESTR: Timer External START ...
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Table 9.2 Configuration Register 6 Description Bit PRESC TMRW 6 7 Figure 9.6 Configuration Register 6 REG_CONF 6 TIMER Name Value 00000 00001 00010 00011 00100 ...
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ST52T400/T440/E440/T441 Table 9.3 Configuration Register 7 Description Bit Name 0 TRST 1 2 TSTR 3 4 TCLK Reset Configuration = “00000000” Figure 9.7 Configuration Register 7 REG_CONF 7 TIMER ...
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TRIAC/PWM DRIVER ST52x400/440/441 offers a peripheral able to generate a TROUT signal on PA0 pin (able to sup- ply mA), to drive an external device, like a TRIAC, an IGBT or a Power MOS. A Triac/PWM ...
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ST52T400/T440/E440/T441 Burst Mode The Burst principle is based on turning the TRIAC device on and off for a fixed integer number of mains voltage periods, in order to control the power transferred to the load. In Burst Mode the peripheral ...
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PWM Mode Settings By using the 16-bit Prescaler (REG_CONF8 and REG_CONF9), the PWM period can be generated by dividing the internal master clock, an external clock signal applied to pin MAIN1, or the mains voltage frequency, using the circuit ...
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ST52T400/T440/E440/T441 10.3 Burst Mode When working in Burst mode, the synchronization with the mains is mandatory, REG_CONF10(4) bit CKSL must be set to “1”. (Table 10.3). A square wave Tb is generated with a duty cycle proportional to the power ...
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In particular, the pulses are generated by using the rising edge of the signal MAIN1 and the falling edge of the signal MAIN2. Figure 10.6 illustrates the generation of the Triac pulses Tp. The first firing pulse for the Triac ...
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ST52T400/T440/E440/T441 of MAIN1. 2) The firing pulse is reset to “0" after the time Tp fixed by program the falling edge of MAIN2 the firing pulse is set to “1" 4) The firing pulse is reset to “0" ...
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Figure 10.8 Phase angle Partialization Mode L N Table 10.3 Configuration Register 10 Bit Name Value 0 0 POL MODE Internal Clock Master 4 CKSL TCST 1 ...
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ST52T400/T440/E440/T441 Figure 10.10 Phase Angle Partialization Zero Crossing Circuit 220 V AC Figure 10.11 TRIAC/PWM Configuration Registers 70/94 A/C – D/C Adaptor 220 k REG_CONF10 TRIAC/PWM POL: Pulses ...
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Figure 10.12 TRIAC/PWM Configuration Registers 19 and REG_CONF19 TRIAC/PWM UTPMSB: Output Pulse Width REG_CONF20 TRIAC/PWM UTPLSB: Output Pulse Width ST52T400/T440/E440/T441 71/94 ...
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ST52T400/T440/E440/T441 11 ELECTRICAL CHARACTERISTICS 11.1 Parameter Conditions Unless otherwise specified, all voltages are referred to V ss. 11.1.1 Minimum and Maximum values. Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of environment temperature, supply ...
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Table 11.1 Voltage Characteristics Symbol Variation between digital and analog ground pins V | SSA DESD Table 11.2 Current Characteristics Symbol I Total current in V VDD I VSS Output current ...
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ST52T400/T440/E440/T441 11.3 Recommended Operating Condition Operating condition: V =5V 10 Table 11.4 Recommended Operating Conditions Symbol Parameter 2) Operating Supply Programming Voltage PP V Output Voltage O V Analog Ground SSA 1)2) Oscillator Frequency f ...
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Supply Current Characteristics Supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the ...
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ST52T400/T440/E440/T441 Table 11.6 Supply Current in HALT Mode Symbol Parameter I Supply current in HALT mode DD Notes: 1. Typical data is based All I/O pins in input mode with a static value at ...
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Clock and Timing Characteristics Operating Conditions: V =5V 5%, TA=0/125 C, unless otherwise specified DD Table 11.8 General Timing Parameters Symbol Parameters f Oscillator Frequency osc t Clock High CLH t Clock Low CLL t Setup SET t Hold ...
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ST52T400/T440/E440/T441 11.7 Memory Characteristics Subject to general operating conditions for V Table 11.9 RAM and Registers Symbol Parameter Data retention mode Table 11.10 EPROM Program Memory Symbol Parameter W UV lamp ERASE 2) t ERASE Erase time ...
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ESD Pin Protection Strategy In order to protect an integrated circuit against Electro-Static Discharge the stress must be controlled to prevent degradation or destruction of the circuit elements. Stress generally affects the circuit elements, which are connected to the ...
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ST52T400/T440/E440/T441 11.9 Port Pin Characteristics 11.9.1 General Characteristics. Subject to general operating condition for V Symbol Parameter CMOS type low level input voltage. Port B pins. (See Fig 11.13 TTL type Schmitt trigger low level input voltage. Port ...
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Subject to general operating conditions for V Table 11.11 Output Voltage Levels Symbol Parameter Output low level voltage for standard I pin when 8 pins are sunk at same time. Output high level voltage for standard I/ ...
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ST52T400/T440/E440/T441 Subject to general operating condition for V Table 11.12 Output Driving Current Symbol Parameter R Input protection resistor S C Pin Capacitance S R Pull-up resistor (*) pu (*) ST52T400 and ST52X440 only Figure 11.12 Port A and Port ...
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Figure 11.14 Port A and Port C pin Equivalent Circuit (ST52T441) Device Input/Output Figure 11.15 Port B Pin Equivalent Circuit (ST52T441) Device Input/Output ...
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ST52T400/T440/E440/T441 11.11 Control Pin Characteristics 11.11.1 RESET pin. Subject to general operating conditions for V Table 11.13 Reset pin Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys t ...
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Analog Comparator Characteristics Operating conditions Table 11.16 Analog Comparator Characteristics Symbol Parameter Res Resolution V Band Gap voltage BG V Input offset voltage OFF Capacitor charging current I CS (measured I (*) fosc = ...
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ST52T400/T440/E440/T441 Table 11.18 S020 PACKAGE MECHANICAL DATA DIM MIN A 2.35 A1 0.1 B 0.33 C 0.23 D 12 0.25 L 0.4 K 86/94 mm TYP. MAX 2.65 0.3 0.51 0.32 13 7.6 1.27 ...
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Table 11.19 SOP28 PACKAGE MECHANICAL DATA DIM MIN A 1.55 a1 0.10 b 0.20 b1 0.18 D 9. 3.80 L 0.40 S 8° mm TYP. MAX 1.75 0.25 0.30 0.25 9.98 6.20 0.64 3.98 0.90 ST52T400/T440/E440/T441 ...
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ST52T400/T440/E440/T441 Table 11.20 PDIP28 PACKAGE MECHANICAL DATA DIM MIN A A1 0.38 A2 3. 0.20 D 36. 13. 15.24 L 3.18 S 1.78 0° N 88/94 mm TYP. MAX 5.08 ...
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Table 11.21 DIP20 PACKAGE MECHANICAL DATA DIM MIN a1 0.508 B 1. TYP. MAX 1.65 0.45 0.25 25.4 8.5 2.54 22.86 7.1 3.93 3.3 1.34 ST52T400/T440/E440/T441 inch. MIN TYP. ...
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ST52T400/T440/E440/T441 Table 11.22 CDIP28W PACKAGE MECHANICAL DATA DIM MIN A A1 0.51 A2 3.91 A3 3. 0.23 D 36. 13. 16.18 L 3.18 S 1.52 4° N 90/94 mm TYP. ...
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Table 11.23 CDIP20W PACKAGE MECHANICAL DATA DIM MIN A A1 0.38 B 3.56 B1 1.14 C 0.20 D 24. 6. 6. TYP. MAX 3.63 0.46 0.56 12.70 1.78 0.25 ...
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ST52T400/T440/E440/T441 ORDERING INFORMATION Each device is available for production in user programmable version (OTP) as well as in factory programmed version (FASTROM). OTP devices are shipped to customers with a default blank con- tent FFh, while FASTROM factory programmed parts ...
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ST52T400/T440/E440/T441 93/94 ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...