PIC18F4585-H/ML Microchip Technology, PIC18F4585-H/ML Datasheet
PIC18F4585-H/ML
Specifications of PIC18F4585-H/ML
Related parts for PIC18F4585-H/ML
PIC18F4585-H/ML Summary of contents
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... PIC18F2585/2680/4585/4680 Enhanced Flash Microcontrollers with ECAN™ Technology, 10-Bit A/D © 2007 Microchip Technology Inc. Data Sheet 28/40/44-Pin and nanoWatt Technology Preliminary DS39625C ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Device Flash # Single-Word (bytes) Instructions (bytes) PIC18F2585 48K 24576 PIC18F2680 64K 32768 PIC18F4585 48K 24576 PIC18F4680 64K 32768 © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 Peripheral Highlights: • High current sink/source 25 mA/25 mA • Three external interrupts • One Capture/Compare/PWM (CCP1) module • Enhanced Capture/Compare/PWM (ECCP1) module ...
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... REF REF REF REF Preliminary RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN9 RB3/CANRX RB2/INT2/CANTX RB1/INT1/AN8 RB0/INT0/AN10 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN9 RB3/CANRX RB2/INT2/CANTX RB1/INT1/AN8 RB0/INT0/FLT0/AN10 RD7/PSP7/P1D RD6/PSP6/P1C RD5/PSP5/P1B RD4/PSP4/ECCP1/P1A RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3/C2IN- RD2/PSP2/C2IN+ © 2007 Microchip Technology Inc. ...
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... RB1/INT1/AN8 RB2/INT2/CANTX RB3/CANRX 44-Pin QFN RC7/RX/DT RD4/PSP4/ECCP1/P1A RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/INT0/FLT0/AN10 RB1/INT1/AN8 RB2/INT2/CANTX © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 PIC18F4585 28 6 PIC18F4680 PIC18F4585 PIC18F4680 Preliminary NC RC0/T1OSO/T13CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 RE2/CS/AN7/C2OUT RE1/WR/AN6/C1OUT RE0/RD/AN5 RA5/AN4/SS/HLVDIN RA4/T0CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 RE2/CS/AN7/C2OUT RE1/WR/AN6/C1OUT RE0/RD/AN5 RA5/AN4/SS/HLVDIN RA4/T0CKI DS39625C-page 3 ...
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... Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 463 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 463 Index .................................................................................................................................................................................................. 465 The Microchip Web Site ..................................................................................................................................................................... 477 Customer Change Notification Service .............................................................................................................................................. 477 Customer Support .............................................................................................................................................................................. 477 Reader Response .............................................................................................................................................................................. 478 PIC18F2585/2680/4585/4680 Product Identification System ............................................................................................................ 479 DS39625C-page 4 Preliminary © 2007 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 Preliminary DS39625C-page 5 ...
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... PIC18F2585/2680/4585/4680 NOTES: DS39625C-page 6 Preliminary © 2007 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC18F2585 • PIC18F2680 • PIC18F4585 • PIC18F4680 This family of devices offers the advantages of all PIC18 microcontrollers – namely, high performance at an economical price – with the addition of high-endurance, Enhanced Flash program memory ...
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... Enhanced Flash memory, designated with an “F” in the part number (such as PIC18F2585), accommodate an operating V Low-voltage parts, designated by “LF” (such as PIC18LF2585), function over an extended V of 2.0V to 5.5V. Preliminary © 2007 Microchip Technology Inc. 64 Kbytes for devices have one (present ...
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... WDT WDT Yes Yes Yes Yes 75 Instructions; 83 with Extended Instruction Set Instruction Set enabled enabled 28-pin PDIP 28-pin PDIP 28-pin SOIC 28-pin SOIC Preliminary PIC18F4585 PIC18F4680 DC – 40 MHz DC – 40 MHz 49152 65536 24576 32768 3328 3328 1024 1024 20 20 Ports Ports ...
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... EUSART 10-bit Preliminary PORTA RA0/AN0 RA1/AN1 RA2/AN2/V - REF RA3/AN3/V + REF RA4/T0CKI RA5/AN4/SS/HLVDIN OSC2/CLKO/RA6 OSC1/CLKI/RA7 PORTB RB0/INT0/AN10 RB1/INT1/AN8 RB2/INT2/CANTX RB3/CANRX RB4/KBI0/AN9 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD PORTC RC0/T1OSO/T13CKI RC1/T1OSI 8 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTE (1) MCLR/V /RE3 PP ECAN © 2007 Microchip Technology Inc. ...
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... FIGURE 1-2: PIC18F4585/4680 (40/44-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic PCLATH PCLATU 21 20 PCU PCH Program Counter 31 Level Stack Address Latch Program Memory STKPTR (48/64 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> IR Instruction Decode & Control Internal (2) OSC1 ...
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... Crystal Oscillator mode. O — mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output I = Input P = Power Preliminary Description © 2007 Microchip Technology Inc. ...
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... T0CKI RA5/AN4/SS/HLVDIN 7 RA5 AN4 SS HLVDIN RA6 RA7 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 Pin Buffer Type Type PORTA is a bidirectional I/O port. I/O TTL Digital I/O. I Analog Analog input 0. ...
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... Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power Preliminary Description © 2007 Microchip Technology Inc. ...
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... RC7 RX DT RE3 — Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O. O — Timer1 oscillator output Timer1/Timer3 external clock input. ...
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... PIC18F2585/2680/4585/4680 TABLE 1-3: PIC18F4585/4680 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP QFN MCLR/V /RE3 MCLR V PP RE3 OSC1/CLKI/RA7 13 32 OSC1 CLKI RA7 OSC2/CLKO/RA6 14 33 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output DS39625C-page 16 ...
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... TABLE 1-3: PIC18F4585/4680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN RA0/AN0/ REF RA0 AN0 CV REF RA1/AN1 3 20 RA1 AN1 RA2/AN2 REF RA2 AN2 V - REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI 6 23 RA4 T0CKI RA5/AN4/SS/HLVDIN 7 24 RA5 AN4 SS HLVDIN ...
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... PIC18F2585/2680/4585/4680 TABLE 1-3: PIC18F4585/4680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN RB0/INT0/FLT0/AN10 33 9 RB0 INT0 FLT0 AN10 RB1/INT1/AN8 34 10 RB1 INT1 AN8 RB2/INT2/CANTX 35 11 RB2 INT2 CANTX RB3/CANRX 36 12 RB3 CANRX RB4/KBI0/AN9 37 14 RB4 KBI0 AN9 RB5/KBI1/PGM 38 15 ...
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... TABLE 1-3: PIC18F4585/4680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN RC0/T1OSO/T13CKI 15 34 RC0 T1OSO T13CKI RC1/T1OSI 16 35 RC1 T1OSI RC2/CCP1 17 36 RC2 CCP1 RC3/SCK/SCL 18 37 RC3 SCK SCL RC4/SDI/SDA 23 42 RC4 SDI SDA RC5/SDO 24 43 RC5 SDO RC6/TX/CK ...
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... PIC18F2585/2680/4585/4680 TABLE 1-3: PIC18F4585/4680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN RD0/PSP0/C1IN RD0 PSP0 C1IN+ RD1/PSP1/C1IN RD1 PSP1 C1IN- RD2/PSP2/C2IN RD2 PSP2 C2IN+ RD3/PSP3/C2IN RD3 PSP3 C2IN- RD4/PSP4/ECCP1 P1A RD4 PSP4 ECCP1 P1A RD5/PSP5/P1B 28 3 RD5 PSP5 P1B ...
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... TABLE 1-3: PIC18F4585/4680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN RE0/RD/AN5 8 25 RE0 RD AN5 RE1/WR/AN6/C1OUT 9 26 RE1 WR AN6 C1OUT RE2/CS/AN7/C2OUT 10 27 RE2 CS AN7 C2OUT RE3 — — V 12 — 13 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels ...
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... PIC18F2585/2680/4585/4680 NOTES: DS39625C-page 22 Preliminary © 2007 Microchip Technology Inc. ...
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... The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of the crystal manufacturer’s specifications. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 FIGURE 2-1: (1) C1 (1) C2 Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2 ...
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... Clock from Ext. System Preliminary EXTERNAL CLOCK INPUT OPERATION (HS OSCILLATOR CONFIGURATION) OSC1 PIC18FXXXX (HS Mode) Open OSC2 EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18FXXXX OSC2/CLKO /4 OSC EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1/CLKI PIC18FXXXX RA6 I/O (OSC2) © 2007 Microchip Technology Inc. ...
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... Recommended values: 3 kΩ ≤ R ≤ 100 kΩ EXT C > EXT © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 2.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator ...
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... Section 2.6.5.1 “Compensating with the EUSART”, Section 2.6.5.2 “Compensating with the Timers” and Section 2.6.5.3 “Compensating with the CCP1 Module in Capture Mode”, but other techniques may be used. Preliminary or temperature changes, which can compensation techniques are © 2007 Microchip Technology Inc. ...
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... If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 (1) U-0 R/W-0 ...
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... MHz 101 1 MHz 100 500 kHz 011 250 kHz FOSC3:FOSC0 010 125 kHz 001 31 kHz 1 000 0 OSCTUNE<7> Preliminary © 2007 Microchip Technology Inc. Peripherals CPU IDLEN Clock Control OSCCON<1:0> Clock Source Option for other Modules WDT, PWRT, FSCM and Two-Speed Startup ...
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... INTRC is providing the clock or the internal oscillator block has just started and is not yet stable. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed ...
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... R = Readable bit -n = Value at POR DS39625C-page 30 (1) R/W-0 R/W-0 R R-0 IRCF1 IRCF0 OSTS IOFS (2) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Feedback inverter disabled at quiescent voltage level Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 real-time clock. Other features may be operating that do not require a device clock source (i.e., SSP slave, PSP, INTn pins and others) ...
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... PIC18F2585/2680/4585/4680 NOTES: DS39625C-page 32 Preliminary © 2007 Microchip Technology Inc. ...
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... Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power managed modes. They are: • ...
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... When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. Preliminary © 2007 Microchip Technology Inc. ...
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... PRI_RUN RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 n-1 n ...
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... The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n Clock Transition (1) PLL (1) OST n-1 n Clock Transition PC OSTS bit set Preliminary © 2007 Microchip Technology Inc. ...
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... Wake Event Note1 1024 (approx). These intervals are not shown to scale. OST OSC PLL © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 3.4 Idle Modes in the The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...
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... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled but not yet run- ning, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD PC Preliminary © 2007 Microchip Technology Inc. ...
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... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/GIEH bit (INTCON< ...
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... CSD (1) INTRC (2) INTOSC T IOBST is the PLL Lock-out Timer (parameter F12 (parameter 39), the INTOSC stabilization period. IOBST Preliminary Clock Ready Status Bit (OSCCON) OSTS (2) — IOFS ( OSTS rc — IOFS (5) ( OSTS rc (2) — IOFS (4) ( OSTS rc (2) — (5) IOFS © 2007 Microchip Technology Inc. ...
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... Ripple Counter Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-2 for time-out situations. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 4-1. ...
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... POR was set to ‘1’ by software immediately after POR). DS39625C-page 42 (1) U-0 R/W-1 R-1 — (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary (2) R-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... If these conditions are not met, the device must be held in Reset until the operating conditions are met. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 POR events are captured by the POR bit (RCON<1>). The state of the bit is set to ‘0’ whenever a POR occurs; ...
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... BOR Operation BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled in software; operation controlled by SBOREN. BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. Preliminary © 2007 Microchip Technology Inc. ...
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... INTIO1, INTIO2 66 ms Note (65.5 ms) is the nominal Power-up Timer (PWRT) delay the nominal time required for the PLL to lock. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 4.5.3 PLL LOCK TIME-OUT With the PLL enabled in its PLL mode, the time-out incorporate sequence following a Power-on Reset is slightly different from other oscillator modes ...
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... PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39625C-page 46 T PWRT T OST T PWRT T OST T PWRT T OST Preliminary © 2007 Microchip Technology Inc RISE < PWRT ): CASE CASE 2 DD ...
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... TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the PWRT timer. T PLL © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 , V RISE > PWRT T OST T PWRT T ...
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... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register SBOREN 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h ( (1) ( Preliminary STKPTR Register POR BOR STKFUL STKUNF © 2007 Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘0’s (a NOP instruction). The PIC18F2585 and PIC18F4585 each have 48 Kbytes of Flash memory and can store up to 24,576 single-word PIC18F4680 each have 64 Kbytes of Flash memory and can store up to 32,768 single-word instructions ...
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... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack <20:0> 11111 11110 11101 TOSL 34h 00011 001A34h 00010 Top-of-Stack 000D58h 00001 00000 Preliminary Stack Pointer STKPTR<4:0> 00010 © 2007 Microchip Technology Inc. ...
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... Note 1: Bit 7 and bit 6 are cleared by user software POR. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 6.1 “Table Reads and Table Writes”. Preliminary COMPUTED GOTO USING AN OFFSET VALUE OFFSET, W TABLE PCL nnh nnh nnh © 2007 Microchip Technology Inc. ...
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... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Preliminary 0006h is encoded in the program Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2007 Microchip Technology Inc. ...
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... SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 5.3.2 “Access Bank” provides a detailed description of the Access RAM. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 5.3.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible ...
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... RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When The BSR specifies the Bank used by the instruction. Access Bank 00h Access RAM Low 5Fh 60h Access RAM High (SFRs) FFh © 2007 Microchip Technology Inc. ...
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... Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’ © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 Data Memory 000h ...
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... LATD RCSTA F8Bh LATC EEADRH F8Ah LATB EEADR F89h LATA EEDATA F88h — (3) F87h — EECON1 F86h — IPR3 F85h — (1) PIR3 F84h PORTE (1) PIE3 F83h PORTD IPR2 F82h PORTC PIR2 F81h PORTB PIE2 F80h PORTA © 2007 Microchip Technology Inc. ...
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... Note 1: Registers available only on PIC18F4X8X devices; otherwise, the registers read as ‘0’. 2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties. 3: This is not a physical register. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 Name Address F5Fh CANCON_RO0 ...
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... E8Bh — — E8Ah — — E89h — — E88h — — E87h — — E86h — — E85h — — E84h — — E83h — — E82h — — E81h — — E80h — © 2007 Microchip Technology Inc. ...
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... Note 1: Registers available only on PIC18F4X8X devices; otherwise, the registers read as ‘0’. 2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties. 3: This is not a physical register. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 Name Address E6Fh CANCON_RO5 ...
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... D8Bh RXF14EIDL — D8Ah RXF14EIDH — D89h RXF14SIDL — D88h RXF14SIDH — D87h RXF13EIDL — D86h RXF13EIDH — D85h RXF13SIDL — D84h RXF13SIDH — D83h RXF12EIDL — D82h RXF12EIDH — D81h RXF12SIDL — D80h RXF12SIDH © 2007 Microchip Technology Inc. ...
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... D60h RXF6SIDH Note 1: Registers available only on PIC18F4X8X devices; otherwise, the registers read as ‘0’. 2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties. 3: This is not a physical register. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 Preliminary DS39625C-page 75 ...
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... N/A 49, 89 N/A 49, 90 N/A 49, 90 N/A 49, 90 N/A 49, 90 49, 89 ---- xxxx 49, 89 xxxx xxxx 50, 67 ---- 0000 N/A 50, 89 N/A 50, 90 N/A 50, 90 N/A 50, 90 N/A 50, 90 50, 89 ---- xxxx 50, 89 xxxx xxxx © 2007 Microchip Technology Inc. ...
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... CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers are available on PIC18F4X8X devices only. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 Bit 4 Bit 3 Bit 2 — ...
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... TRISE1 TRISE0 0000 -111 52, 141 1111 1111 52, 138 1111 1111 52, 135 1111 1111 52, 132 1111 1111 52, 129 LATE1 LATE0 ---- -xxx 52, 141 xxxx xxxx 52, 138 xxxx xxxx 52, 135 xxxx xxxx 52, 132 xxxx xxxx 52, 129 © 2007 Microchip Technology Inc. ...
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... CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers are available on PIC18F4X8X devices only. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 Bit 4 Bit 3 Bit 2 ...
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... TXB1D31 TXB1D30 xxxx xxxx 54, 284 TXB1D21 TXB1D20 xxxx xxxx 54, 284 TXB1D11 TXB1D10 xxxx xxxx 54, 284 TXB1D01 TXB1D00 xxxx xxxx 54, 284 DLC1 DLC0 -x-- xxxx 54, 285 EID1 EID0 xxxx xxxx 54, 284 EID9 EID8 xxxx xxxx 54, 283 © 2007 Microchip Technology Inc. ...
Page 83
... CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers are available on PIC18F4X8X devices only. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 Bit 4 Bit 3 Bit 2 — ...
Page 84
... B4D41 B4D40 xxxx xxxx 56, 299 B4D31 B4D30 xxxx xxxx 56, 299 B4D21 B4D20 xxxx xxxx 56, 299 B4D11 B4D10 xxxx xxxx 56, 299 B4D01 B4D00 xxxx xxxx 56, 299 DLC1 DLC0 -xxx xxxx 56, 300 DLC1 DLC0 -x-- xxxx 56, 301 © 2007 Microchip Technology Inc. ...
Page 85
... CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers are available on PIC18F4X8X devices only. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 Bit 4 Bit 3 Bit 2 ...
Page 86
... B0D61 B0D60 xxxx xxxx 58, 299 B0D51 B0D50 xxxx xxxx 58, 299 B0D41 B0D40 xxxx xxxx 58, 299 B0D31 B0D30 xxxx xxxx 58, 299 B0D21 B0D20 xxxx xxxx 58, 299 B0D11 B0D10 xxxx xxxx 58, 299 B0D01 B0D00 xxxx xxxx 58, 299 © 2007 Microchip Technology Inc. ...
Page 87
... CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers are available on PIC18F4X8X devices only. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 Bit 4 Bit 3 Bit 2 ...
Page 88
... SID3 xxxx xxxx 60, 303 EID0 xxxx xxxx 60, 303 EID8 xxxx xxxx 60, 303 EID16 xxx- x-xx 60, 304 SID3 xxxx xxxx 60, 303 EID0 xxxx xxxx 60, 303 EID8 xxxx xxxx 60, 303 EID16 xxx- x-xx 60, 304 SID3 xxxx xxxx 60, 303 © 2007 Microchip Technology Inc. ...
Page 89
... Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the bits in the STATUS register ...
Page 90
... Example 5-5. EXAMPLE 5-5: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING LFSR FSR0, 100h ; NEXT CLRF POSTINC0 BTFSS FSR0H, 1 BRA NEXT CONTINUE Preliminary © 2007 Microchip Technology Inc. ; Clear INDF ; register then ; inc pointer ; All done with ; Bank1? ; NO, clear next ; YES, continue ...
Page 91
... ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 mapped in the SFR space, but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair ...
Page 92
... Similarly, operations by indirect addressing are gener- ally permitted on all other SFRs. Users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. Preliminary © 2007 Microchip Technology Inc. ...
Page 93
... This special addressing mode is known as Indexed Addressing with Literal Offset or Indexed Literal Offset mode. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 When using the extended instruction set, this addressing mode requires the following: • ...
Page 94
... F00h Bank 15 F60h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 080h 100h 001001da Bank 1 through Bank 14 F00h Bank 15 F60h SFRs FFFh Data Memory Preliminary © 2007 Microchip Technology Inc. 00h 60h Valid range for ‘f’ FFh ffffffff FSR2L ffffffff ...
Page 95
... F00h BSR. F60h FFFh © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use direct addressing as before. Any indirect or ...
Page 96
... PIC18F2585/2680/4585/4680 NOTES: DS39625C-page 94 Preliminary © 2007 Microchip Technology Inc. ...
Page 97
... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 98
... The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Note: The EEIF Interrupt flag bit (PIR2<4>) is set when the write is complete. It must be cleared in software. When set, Preliminary Table Latch (8-bit) TABLAT © 2007 Microchip Technology Inc. ...
Page 99
... Initiates an EEPROM read (Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 U-0 R/W-0 R/W-x — ...
Page 100
... TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TBLPTR<21:6> TABLE READ – TBLPTR<21:0> Preliminary TBLPTRL 0 TABLE WRITE TBLPTR<5:0> © 2007 Microchip Technology Inc. ...
Page 101
... WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVF WORD_ODD © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 102
... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Preliminary © 2007 Microchip Technology Inc. ...
Page 103
... Set the EECON1 register for the write operation: • set EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN to enable byte writes. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle ...
Page 104
... TBLWT holding register. ; loop until buffers are full Preliminary © 2007 Microchip Technology Inc. ...
Page 105
... CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: These bits are available in PIC18F4X8X devices and reserved in PIC18F2X8X devices. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 ; point to Flash program memory ; access Flash program memory ; enable write to memory ...
Page 106
... PIC18F2585/2680/4585/4680 NOTES: DS39625C-page 104 Preliminary © 2007 Microchip Technology Inc. ...
Page 107
... EECON1 and EECON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 The EECON1 register (Register 7-1) is the control register for data and program memory access. Control bit EEPGD determines if the access will be to program or data EEPROM memory ...
Page 108
... Legend Readable bit -n = Value at POR DS39625C-page 106 U-0 R/W-0 R/W-x R/W-0 — FREE WRERR WREN W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/S-0 R/S bit Bit is unknown ...
Page 109
... BSF EECON1, WR BSF INTCON, GIE BCF EECON1, WREN © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM ...
Page 110
... Loop to refresh array ; Read current address ; ; Write 55h ; ; Write 0AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; Increment the high address ; Not zero again ; Disable writes ; Enable interrupts Preliminary information (e.g., program © 2007 Microchip Technology Inc. ...
Page 111
... CMIF (1) PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: These bits are available in PIC18F4X8X devices and reserved in PIC18F2X8X devices. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — ...
Page 112
... PIC18F2585/2680/4585/4680 NOTES: DS39625C-page 110 Preliminary © 2007 Microchip Technology Inc. ...
Page 113
... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 EXAMPLE 8-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 8-2: MOVF ARG1, W MULWF ARG2 ...
Page 114
... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2007 Microchip Technology Inc. ...
Page 115
... Individual inter- rupts can be disabled through their corresponding enable bits. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 When the IPEN bit is cleared (default state), the inter- rupt priority feature is disabled and interrupts are com- ® ...
Page 116
... INT2IF INT2IE INT2IP IPE IPEN GIEL/PEIE IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Preliminary © 2007 Microchip Technology Inc. Wake- Sleep Mode Interrupt to CPU Vector to Location 0008h GIEH/GIE Interrupt to CPU Vector to Location 0018h GIEL/PEIE GIE/GEIH ...
Page 117
... A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
Page 118
... This feature allows for software polling. DS39625C-page 116 R/W-1 R/W-1 U-0 R/W-1 INTEDG1 INTEDG2 — TMR0IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 R/W-1 — RBIP bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 119
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 U-0 R/W-0 R/W-0 — ...
Page 120
... R-0 R-0 R/W-0 R/W-0 RCIF TXIF SSPIF CCP1IF ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
Page 121
... A TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Unused in this mode. Note 1: These bits are available in PIC18F4X8X and reserved in PIC18F2X8X devices. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 U-0 R/W-0 R/W-0 (1) — EEIF ...
Page 122
... TXB0IF R/W-0 R/W-0 R/W-0 R/W-0 (1) ERRIF TXBnIF TXB1IF TXB0IF (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 (1) RXB1IF RXB0IF R/W-0 R/W-0 (1) RXBnIF FIFOWMIF bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 123
... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 R/W-0 R/W-0 R/W-0 ADIE RCIE TXIE SSPIE W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 124
... R = Readable bit -n = Value at POR DS39625C-page 122 U-0 R/W-0 R/W-0 (1) — EEIE BCLIE (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 R/W-0 (2) HLVDIE TMR3IE ECCP1IE bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 125
... When CAN is in Mode 2: FIFOWMIE: FIFO Watermark Interrupt Enable bit 1 = Enable FIFO watermark interrupt 0 = Disable FIFO watermark interrupt Note 1: In CAN Mode 1 and 2, this bit is forced to ‘0’. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 R/W-0 R/W-0 R/W-0 R/W-0 (1) ERRIE ...
Page 126
... R = Readable bit -n = Value at POR DS39625C-page 124 R/W-1 R/W-1 R/W-1 R/W-1 RCIP TXIP SSPIP CCP1IP ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 127
... ECCP1IP: ECCP1 Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: This bit is available in PIC18F4X8X devices and reserved in PIC18F2X8X devices. 2: This bit is available in PIC18F4X8X devices only. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 U-0 R/W-1 R/W-1 (1) — EEIP ...
Page 128
... TXB0IP R/W-1 R/W-1 R/W-1 R/W-1 (1) ERRIP TXBnIP TXB1IP TXB0IP (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 (1) RXB1IP RXB0IP R/W-1 R/W-1 (1) RXBnIP FIFOWMIP bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 129
... POR: Power-on Reset Status bit For details of bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 U-0 U-0 R/W-1 R-1 — RI ...
Page 130
... Example 9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS Preliminary © 2007 Microchip Technology Inc. ...
Page 131
... Port Note 1: I/O pins have diode protection to V © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 10.1 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
Page 132
... Main oscillator input connection, determined by FOSC3:FOSC0 x Configuration bits. Enabling OSC1 overrides digital I/O. ANA Main clock input connection, determined by FOSC3:FOSC0 x Configuration bits. Enabling CLKI overrides digital I/O. DIG LATA<7> data output. 0 TTL PORTA<7> data input. 1 Preliminary Description /4). OSC © 2007 Microchip Technology Inc. ...
Page 133
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. 2: These registers are unimplemented on PIC18F2X8X devices. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 Bit 5 Bit 4 Bit 3 Bit 2 ...
Page 134
... Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. Preliminary © 2007 Microchip Technology Inc. ...
Page 135
... KBI3 IN PGD OUT IN Legend: PWR = Power Supply; OUT = Output Input; ANA = Analog Signal; DIG = Digital Output Schmitt Buffer Input; TTL – TTL Buffer Input © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 TRIS Buffer DIG LATB<0> data output. 0 TTL PORTB<0> data input. Weak pull-up available only in this mode. ...
Page 136
... Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 INT0IE RBIE TMR0IF — TMR0IP — INT2IE INT1IE — VCFG1 VCFG0 PCFG3 PCFG2 Preliminary Reset Bit 1 Bit 0 Values on page RB1 RB0 INT0IF RBIF 49 — RBIP 49 INT2IF INT1IF 49 PCFG1 PCFG0 50 © 2007 Microchip Technology Inc. ...
Page 137
... TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 Note Power-on Reset, these pins are configured as digital inputs ...
Page 138
... EUSART synchronous clock input. DIG LATC<7> data output. ST PORTC<7> data input. ST EUSART asynchronous data input. DIG EUSART synchronous data output – must have TRIS set to ‘1’ to enable EUSART to control the bidirectional communication. ST EUSART synchronous data input. Preliminary © 2007 Microchip Technology Inc. ...
Page 139
... TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC PORTC Data Output Register TRISC PORTC Data Direction Register © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 Preliminary Reset Bit 1 Bit 0 ...
Page 140
... EXAMPLE 10-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs Preliminary © 2007 Microchip Technology Inc. ...
Page 141
... IN x P1D OUT 0 Legend: PWR = Power Supply; OUT = Output Input; ANA = Analog Signal; DIG = Digital Output Schmitt Buffer Input; TTL = TTL Buffer Input © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 Buffer Description DIG LATD<0> data output. ST PORTD<0> data input. DIG Parallel Slave Port (PSP) data output (overrides the TRIS<0> control when enabled). ...
Page 142
... These registers are available on PIC18F4X8X devices only. DS39625C-page 140 Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 IBOV PSPMODE — PORTE Data Direction bits EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 Preliminary Reset Bit 1 Bit 0 Values on page RD1 RD0 © 2007 Microchip Technology Inc. ...
Page 143
... The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register, read and write the latched output value for PORTE. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 The fourth pin of PORTE (MCLR/V only pin. Its operation is controlled by the MCLRE Configuration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input only pin ...
Page 144
... Value at POR DS39625C-page 142 R-0 R/W-0 R/W-0 U-0 OBF IBOV PSPMODE — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 R/W-1 TRISE2 TRISE1 TRISE0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 145
... RE3 is the only PORTE bit implemented on both PIC18F2X8X and PIC18F4X8X devices. All other bits are implemented only when PORTE is implemented (i.e., PIC18F4X8X devices). 3: These registers are unimplemented on PIC18F2X8X devices. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 TRIS Buffer DIG LATE<0> data output. ...
Page 146
... Set Interrupt Flag PSPIF (PIR1<7>) Note: I/O pins have diode protection to V Preliminary PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) One bit of PORTD D Q RDx pin CK TTL PORTE Pins Read RD TTL Chip Select CS TTL Write WR TTL and © 2007 Microchip Technology Inc. ...
Page 147
... CMCON C2OUT C1OUT Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Note 1: These registers are available on PIC18F4X8X devices only. 2: These registers are unimplemented on PIC18F2X8X devices and read as ‘ © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 ...
Page 148
... PIC18F2585/2680/4585/4680 NOTES: DS39625C-page 146 Preliminary © 2007 Microchip Technology Inc. ...
Page 149
... Prescale value Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1 ...
Page 150
... Sync with Internal Clocks Delay Preliminary ). There is a delay between OSC Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0L TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2007 Microchip Technology Inc. ...
Page 151
... T08BIT TRISA — PORTA Data Direction Register Legend unknown unchanged, — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution ...
Page 152
... PIC18F2585/2680/4585/4680 NOTES: DS39625C-page 150 Preliminary © 2007 Microchip Technology Inc. ...
Page 153
... Enables Timer1 0 = Stops Timer1 Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 154
... Special Event Trigger) Preliminary 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus © 2007 Microchip Technology Inc. ...
Page 155
... T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 12-1 for additional information about capacitor selection. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type Freq LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 156
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. Preliminary a special event trigger © 2007 Microchip Technology Inc. ...
Page 157
... Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented on PIC18F2X8X devices; always maintain these bits clear. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 ; Preload TMR1 register pair ; for 1 second overflow ...
Page 158
... PIC18F2585/2680/4585/4680 NOTES: DS39625C-page 156 Preliminary © 2007 Microchip Technology Inc. ...
Page 159
... T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 2-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by- 16 prescale options ...
Page 160
... Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TXIF SSPIF CCP1IF TXIE SSPIE CCP1IE TXIP SSPIP CCP1IP Preliminary Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 49 TMR2IF TMR1IF 52 TMR2IE TMR1IE 52 TMR2IP TMR1IP © 2007 Microchip Technology Inc. ...
Page 161
... Enables Timer3 0 = Stops Timer3 Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1) ...
Page 162
... TCCPx Preliminary 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR3H 8 8 Internal Data Bus © 2007 Microchip Technology Inc. ...
Page 163
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. Note 1: These bits are available in PIC18F4X8X devices only. 2: These bits are available in PIC18F4X8X devices and reserved in PIC18F2X8X devices. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h ...
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... PIC18F2585/2680/4585/4680 NOTES: DS39625C-page 162 Preliminary © 2007 Microchip Technology Inc. ...
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... CAPTURE/COMPARE/PWM (CCP1) MODULES PIC18F2585/2680 devices have one CCP1 module. PIC18F4585/4680 devices have (Capture/Compare/PWM) modules. CCP1, discussed in this chapter, implements standard Capture, Compare and Pulse-Width Modulation (PWM) modes. ECCP1 implements an Enhanced PWM mode. The ECCP1 implementation is discussed in Section 16.0 “Enhanced Capture/Compare/PWM Module” ...
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... PWM) at the same time. The interactions between the two modules are summarized in Figure 15-1 and Figure 15-2. Interaction Preliminary © 2007 Microchip Technology Inc. Timer Resource Timer1 or Timer3 Timer1 or Timer3 Timer2 ...
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... CCP1IE or ECCP1IE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCP1IF or ECCP1IF, should also be cleared following any such change in operating mode. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 15.2.4 CCP1 PRESCALER There are four prescaler settings in Capture mode; they are specified as part of the operating mode selected by the mode select bits (CCP1M3:CCP1M0) ...
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... T3ECCP1 and Edge Detect T3ECCP1 4 Set ECCP1IF 4 4 T3CCP1 T3ECCP1 and Edge Detect T3ECCP1 T3CCP1 Preliminary TMR3H TMR3L TMR3 Enable CCPR1H CCPR1L TMR1 Enable TMR1H TMR1L TMR3H TMR3L TMR3 Enable ECCPR1H ECCPR1L TMR1 Enable TMR1H TMR1L © 2007 Microchip Technology Inc. ...
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... TMR3H TMR3L T3CCP1 Comparator ECCPR1H ECCPR1L © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 15.3.2 TIMER1/TIMER3 MODE SELECTION Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the CCP1 module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. ...
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... Preliminary Reset Bit 1 Bit 0 Values on page INT0IF RBIF 49 POR BOR 50 TMR2IP TMR1IP 52 TMR2IF TMR1IF 52 TMR2IE TMR1IE 52 (2) TMR3IP ECCP1IP 51 (2) TMR3IF ECCP1IF 52 (2) TMR3IE ECCP1IE TMR1CS TMR1ON TMR3CS TMR3ON CCP1M1 CCP1M0 ’. 0 © 2007 Microchip Technology Inc. ...
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... A PWM output (Figure 15-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 FIGURE 15-4: Duty Cycle TMR2 = PR2 15 ...
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... ONLY) The PWM auto-shutdown features of the Enhanced CCP1 module are available to PIC18F4585/4680 (40/44-pin) devices. The operation of this feature is discussed in detail in Section 16.4.7 “Enhanced PWM Auto-Shutdown”. Auto-shutdown features are not available for CCP1. DS39625C-page 170 EQUATION 15-3: PWM Resolution (max) = ...
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... EPWM1M1 EPWM1M0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. Note 1: These registers are unimplemented on PIC18F2X8X devices. 2: The SBOREN bit is only available when CONFIG2L<1:0> = © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INT0IE ...
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... PIC18F2585/2680/4585/4680 NOTES: DS39625C-page 172 Preliminary © 2007 Microchip Technology Inc. ...
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... CCP1 module with Enhanced PWM capabilities. These include the provision for output channels, user selectable polarity, dead-band control and automatic shutdown and restart. The REGISTER 16-1: ECCP1CON REGISTER (ECCP1 MODULE, PIC18F4585/4680 DEVICES) R/W-0 EPWM1M1 EPWM1M0 EDC1B1 bit 7 bit 7-6 ...
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... Section 16.4.9 “Setup for PWM Operation”. The latter is more generic but will work for either single or multi-output PWM. RD4 RD5 All PIC18F4585/4680 devices: CCP1 RD5/PSP5 P1A P1B P1A P1B Preliminary up ...
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... ECCP1 pin and latch D.C. PR2 Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 16.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register ...
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... The general relationship of the outputs in all configurations is summarized in Figure 16-2. 9.77 kHz 39.06 kHz FFh FFh Preliminary OSC log F PWM bits log(2) 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 © 2007 Microchip Technology Inc. ...
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... Prescale Value) OSC • Duty Cycle = T * (ECCPR1L<7:0>:ECCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note1: Dead-band delay is programmed using the ECCP1DEL register (Section 16.4.6 “Programmable Dead-Band Delay”). © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 0 Duty Cycle Period (1) (1) Delay ...
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... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. V+ FET Driver P1A Load FET Driver P1B V- V+ FET Driver Load FET Driver V- Preliminary HALF-BRIDGE PWM OUTPUT Period td (1) ( FET Driver FET Driver © 2007 Microchip Technology Inc. ...
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... P1D (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 P1A, P1B, P1C and P1D outputs are multiplexed with the PORTD<4>, PORTD<7> data latches. The TRISD<4>, TRISD<5>, TRISD<6> and TRISD<7> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs ...
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... Reduce PWM for a PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. Preliminary QC FET Driver FET Driver QD © 2007 Microchip Technology Inc. ...
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... All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 (1) Period DC (Note depending on the Timer2 prescaler value. The modulated P1B and OSC Forward Period ...
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... OSC OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary a low level on the driving). The ECCPASE bit R/W-0 R/W-0 R/W-0 (1) (1) (1) PDC2 PDC1 PDC0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Pins B and D tri-state 01 = Drive Pins B and D to ‘1’ Drive Pins B and D to ‘0’ Note 1: Reserved on PIC18F2X8X devices; maintain these bits clear. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 R/W-0 R/W-0 R/W-0 R/W Writable bit U = Unimplemented bit, read as ‘0’ ...
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... PWM period begins. PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears Preliminary PWM Resumes ECCPASE Cleared by Firmware PWM Resumes © 2007 Microchip Technology Inc. ...
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... Wait until TMRn overflows (TMRnIF bit is set). • Enable the ECCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 16.4.10 EFFECTS OF A RESET Both Power-on Reset and subsequent Resets will force all ports to Input mode and the CCP1 registers to their Reset states ...
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... Bit 1 Bit 0 Values on page INT0IF RBIF 49 PD POR BOR 50 TMR2IP TMR1IP 52 TMR2IF TMR1IF 52 TMR2IE TMR1IE 52 (3) TMR3IP ECCP1IP 51 (3) TMR3IF ECCP1IF 51 (3) TMR3IE ECCP1IE TMR1CS TMR1ON 50 50 T2CKPS0 TMR3CS TMR3ON (2) (2) PSSBD0 51 (2) (2) (2) PDC1 PDC0 51 © 2007 Microchip Technology Inc. ...
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... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four ...
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... During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R-0 R-0 CKE D Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R-0 R-0 R-0 R bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved or implemented mode only. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 /64 OSC ...
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... Example 17-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP status register (SSPSTAT) indicates the various status conditions. Preliminary © 2007 Microchip Technology Inc. ...
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... Serial Input Buffer (SSPBUF) Shift Register (SSPSR) LSb MSb PROCESSOR 1 © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 17.3.4 TYPICAL CONNECTION Figure 17-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock ...
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... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 5 bit 4 bit 2 bit 1 bit 3 bit 5 bit 4 bit 3 bit 2 bit 1 Preliminary ) Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2007 Microchip Technology Inc. ...
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... SSPIF Interrupt Flag SSPSR to SSPBUF © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output ...
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... Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS39625C-page 194 bit 6 bit 3 bit 2 bit 5 bit 4 bit 6 bit 5 bit 4 bit 2 bit 3 Preliminary bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2007 Microchip Technology Inc. ...
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... CKE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. Note 1: These bits are unimplemented in PIC18F2X8X devices; always maintain these bits clear. © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 17.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer ...
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... SSPIF interrupt is set. Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT reg) Preliminary 2 C operation mode operation. The 2 C Slave mode. When © 2007 Microchip Technology Inc. ...
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... Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F2585/2680/4585/4680 2 C MODE) R-0 R-0 ...
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... CKP SSPM3 SSPM2 2 /(4 * (SSPADD + 1)) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 R/W-0 SSPM1 SSPM0 bit 0 C conditions were not valid for x = Bit is unknown © 2007 Microchip Technology Inc. ...