MCP3903-I/SS Microchip Technology, MCP3903-I/SS Datasheet
MCP3903-I/SS
Specifications of MCP3903-I/SS
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MCP3903-I/SS Summary of contents
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... Direct Memory Access (DMA MCU and with separate Data Ready pins that can directly be connected to the Interrupt Request (IRQ) input of an MCU. The MCP3903 is capable of interfacing to a large variety of voltage and current sensors including shunts, current transformers, Rogowski coils, and Hall-effect sensors ...
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... MCP3903 Functional Block Diagram REFIN/OUT+ Voltage VREFEXT Reference + V REF - REFIN - REF CH0+ + CH0- - PGA CH1+ + CH1- - PGA DUAL DS ADC CH2+ + CH2- - PGA CH3+ + CH3- - PGA DUAL DS ADC CH4+ + CH4- - PGA CH5+ + CH5- - PGA DUAL DS ADC POR AV DD Monitoring DS25048B-page AMCLK DMCLK/DRCLK ...
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... V ) REF- 1.9 — 2.9 -0.3 — +0.3 24 See Table 4-2 See Table 4 2.4V. RMS REF MCP3903 ........-0. +0.6V GND DD ..................................... ....-6V to +6V GND ................................-0. +0.6V GND DD = 4.5 to 5.5V 2 15.625 ksps -40°C to +125° Units Test Conditions V VREFEXT = 0 ppm/°C VREFEXT = 0 kΩ ...
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... MCP3903 TABLE 1-1: ANALOG SPECIFICATIONS TARGET TABLE Electrical Specifications: Unless otherwise indicated, all parameters apply at AV 3.6V, Internal V , MCLK = 4 MHz;PRESCALE = 1; OSR = 64; f REF GAIN = 353mV @ 50/60 Hz RMS Param. Symbol Characteristic Num. A011 CHn+- Analog Input Absolute Voltage A012 A Analog Input Leakage ...
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... V = 2.4V. RMS REF MCP3903 = 4.5 to 5.5V 2 -40°C to +125°C, A Test Conditions (Note 8) BOOST bits low on all chan- nels BOOST bits high on all channels DV = 3.6V, MCLK = DD 4 MHz DV = 3.6V, MCLK = DD 8.192 MHz -40° ...
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... MCP3903 1.2 SERIAL INTERFACE CHARACTERISTICS SERIAL INTERFACE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all parameters apply 2.7 to 3.6V, -40°C < T <+125° Parameters Serial Clock frequency CS setup time CS hold time CS disable time Data setup time Data hold time Serial Clock high time ...
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... A -65 — +150 A — 71 — must not exceed the absolute maximum specification of +150° Don’t Care f SCK HI-Z MCP3903 = 4.5 to 5.5V 2 Units Conditions °C (Note 1) °C °C/W t CSH Mode 1,1 Mode 0,0 t DIS LSB out t CSD t CLE t t ...
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... Timing Waveform for MDAT0/1 Modulator Output OSC1/CLKI MDAT0/1 FIGURE 1-4: Specific Timing Diagrams. CLKEXT Digital Buffer 1 OSC1 0 OSC2 Multiplexer Crystal Oscillator FIGURE 1-5: MCP3903 Clock Detail. DS25048B-page DRCLK Timing Waveform for SDO t DOMDAT PRESCALE<1:0> Prescale MCLK AMCLK Clock Divider Clock Divider ...
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... FIGURE 2-1: Spectral Response. FIGURE 2-2: Spectral Response. FIGURE 2-3: Spectral Response. © 2011 Microchip Technology Inc. = 5.0V 3.3 V; Internal REF A = -0.5 dBFS @ 60 Hz. IN FIGURE 2-4: FIGURE 2-5: FIGURE 2-6: MCP3903 = +25°C, MCLK = 4 MHz; PRESCALE Spectral Response. Spectral Response. Spectral Response. DS25048B-page 9 ...
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... MCP3903 Note: Unless otherwise indicated 64; GAIN = 1; Dithering OFF -0.5 dBFS @ 60 Hz FIGURE 2-7: Spectral Response. 120 120 120 120 120 120 120 Dithering ON Dithering ON Dithering ON Dithering ON Dithering ON Dithering ON Dithering ON 100 100 100 100 100 100 Dithering OFF Dithering OFF Dithering OFF ...
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... FIGURE 2-17: Distortion vs. Input Signal Amplitude. fs=15 625KHz fs=15.625KHz fs=15.625KHz fs=15.625KHz OSR=64 OSR=64 OSR=64 1000 2000 1000 2000 FIGURE 2-18: Distortion vs. Master Clock. MCP3903 fs=15.625KHz fs=15.625KHz fs=15.625KHz fs=15.625KHz fs=15.625KHz fs=15.625KHz fs=15.625KHz OSR=64 OSR=64 OSR=64 OSR=64 OSR=64 OSR=64 -20 -20 ...
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... MCP3903 Note: Unless otherwise indicated 64; GAIN = 1; Dithering OFF -0.5 dBFS @ 60 Hz. IN 1.40 1.40 1.40 1.40 1.40 1.40 1.40 G=8 G=8 G=8 G=8 G=8 G=8 G=8 1.20 1.20 1.20 1. 1.20 1.20 G=1 G=1 G=1 G=1 G=1 G=1 1.00 1.00 1.00 1.00 1.00 1 ...
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... MCLK Frequency(MHz) MCLK Frequency(MHz) FIGURE 2-27: Operating Current vs. Master Clock (MCLK). © 2011 Microchip Technology Inc. = 5.0V 3 +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = DD A CH0 CH0 CH0 CH0 CH0 CH0 CH0 0.25 0.25 0.5 0.5 0.25 0.25 0.5 0 MCP3903 DS25048B-page 13 ...
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... RESET rising edge. This input is Schmitt triggered. 3.2 Digital V ( the power supply pin for the digital circuitry DD within the MCP3903. This pin requires appropriate bypass capacitors and should be maintained between 2.7V and 3.6V for specified operation. © 2011 Microchip Technology Inc. ...
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... Analog V ( the power supply pin for the analog circuitry DD within the MCP3903. This pin requires appropriate bypass capacitors and should be maintained to 5V ±10% for specified operation. 3.4 ADC Differential Analog Inputs(CHn+/CHn-) CHn- and CHn+, are the two fully-differential analog voltage inputs for the Delta-Sigma ADCs. There are six channels in total grouped in three channel pairs ...
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... This is the serial clock pin for SPI communication. Data is clocked into the device on the RISING edge of SCK. Data is clocked out of the device on the FALLING edge of SCK. The MCP3903 interface is compatible with both SPI 0,0 and 1,1 modes. The maximum clock speed specified is 10 MHz. This input is Schmitt triggered ...
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... OSR - Oversampling Ratio Offset Error Gain Error Integral Non-Linearity Error Signal-To-Noise Ratio (SNR) Signal-To-Noise Ratio And Distortion (SINAD) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) MCP3903 Delta-Sigma Architecture Idle Tones Dithering Crosstalk PSRR CMRR ADC Reset Mode Hard Reset Mode (RESET = 0) ...
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... The specification incorporates both PGA and ADC gain error contributions, but not the V contribution (it is measured with an external V error varies with PGA and OSR settings. The gain error on the MCP3903 has a low temperature coefficient. See the typical performance curves for more information. DRCLK ...
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... DC input signal. 4.9 Signal-To-Noise Ratio (SNR) For the MCP3903 ADC, the signal-to-noise ratio is a ratio of the output fundamental signal power to the noise power (not including the harmonics of the signal), when the input is a sinewave at a predetermined frequency ...
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... DAC is no more simple to realize and its linearity limits the THD of such ADCs. The MCP3903’s 5-level quantizer is a flash ADC composed of 4 comparators arranged with equally spaced thresholds and a thermometer coding. The MCP3903 also includes proprietary 5-level DAC architecture that is inherently linear for improved THD figures ...
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... Where V = (CHn+ + CHn-)/2 is the Common-Mode CM input voltage and V that the output code translates to with the ADC transfer function. In the MCP3903 specification, VCM varies from -1V to +1V, and for AC specification a 50/60 Hz sinewave is chosen centered around 0V with a 500 mV amplitude. 4.19 ADC Reset Mode ADC Reset mode (called also soft reset mode) can only ⎞ ...
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... In this mode, all internal registers are reset to their default state. The DC biases for the analog blocks are still active, i.e. the MCP3903 is ready to convert. However, this pin clears all conversion data in the ADCs. The comparator outputs of all ADCs are forced to their reset state (0011) ...
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... Microchip Technology Inc. 5.3 Delta-Sigma Modulator 5.3.1 ARCHITECTURE All ADCs are identical in the MCP3903 and they include a second-order modulator with a multi-bit DAC architecture (see ADC composed of 4 comparators with equally spaced thresholds and a thermometer output coding. The proprietary 5-level architecture ensures minimum ...
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... MCP3903 5.3.2 MODULATOR INPUT RANGE AND SATURATION POINT For a specified voltage reference value of 2.4V, the modulator specified differential input range is ±500 mV. The input range is proportional to V according to the V voltage. This range ensures the REF stability of the modulator over amplitude and frequency. ...
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... SINC Filter All ADCs present in the MCP3903 include a decimation filter that is a third-order sinc (or notch) filter. This filter processes the multi-bit bitstream into bits words (depending on the WIDTH configuration bit). The settling time of the filter is 3 DMCLK periods recommended to discard unsettled data to avoid data corruption which can be done easily by setting the DR_LTY bit high in the STATUS/COM register ...
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... MCP3903 5.5 ADC OUTPUT CODING 3 The second order modulator, SINC filter, PGA, V and analog input structure all work together to produce the device transfer function for the analog to digital con- version, shown in Equation 5-3. The channel data is either a 16-bit or 24-bit word, presented in 23-bit or 15-bit plus sign, two’s complement format and is MSB (left) justified ...
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... Voltage Reference 5.6.1 INTERNAL VOLTAGE REFERENCE The MCP3903 contains an internal voltage reference source specially designed to minimize drift over temperature. In order to enable the internal voltage reference, the VREFEXT bit in the configuration register must be set to 0 (default mode). This internal V supplies reference voltage to both channels. The REF typical value of this voltage reference is 2.35V ± ...
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... MCP3903 5.7 Power-on Reset The MCP3903 contains an internal POR circuit that monitors analog supply voltage AV during operation. DD The typical threshold for a power-up event detection is 4.2V ±5%. The POR circuit has a built-in hysteresis for improved transient spikes immunity that has a typical value of 200 mV. Proper decoupling capacitors (0.1 µF ceramic and 10 µ ...
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... Microchip Technology Inc. 5.10 Crystal Oscillator The MCP3903 includes a Pierce-type crystal oscillator with very high stability and ensures very low tempco and jitter for the clock generation. This oscillator can handle up to 16.384 MHz crystal frequencies, provided that proper load capacitances and quartz quality factor are used ...
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... OVERVIEW The MCP3903 device is compatible with SPI modes 0,0 and 1,1. Data is clocked out of the MCP3903 on the falling edge of SCK, and data is clocked into the MCP3903 on the rising edge of SCK. In these modes, SCK can idle either high or low. Each SPI communication starts with a CS falling edge and stops with the CS rising edge ...
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... Device Write (SPI Mode 0,0 - Clock Idles Low). 6.6 SPI MODE 1,1 - Clock Idle High, Read/Write Examples In this SPI mode, the clock idles High. For the MCP3903, this means that there will be a falling edge before there is a rising edge. CS DATA TRANSITIONS ON THE FALLING EDGE ...
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... LOOPING ON ADDRESS SETS If the user wishes to read back any of the ADC channels continuously, or all channels continuously, the internal address counter of the MCP3903 can be set to loop on specific register sets. In this case, there is only one control byte on SDI to start the communication. The part stays within the same loop until CS returns high ...
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... ADC without using the RESET bits in the configuration register. 6.9 Line Cycle Sampling Options Since the AMCLK range can MHz, the MCP3903 is able to accommodate 256 output samples per line cycles with line frequencies up to 76.2Hz at OSR=64. . TABLE 6-1: ...
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... MCP3903 DATA LINE OSC1/MCLKI DATA DRn CS SCK SDI SDO FIGURE 6-7: Standard Device Operation. 6.10 Data Ready Pulses (DRn) To ensure that all channel ADC data are present at the same time for SPI read, regardless of phase delay set- tings for either or both channels, there are two sets of latches in series with both the data ready and the ‘ ...
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... PHASE < 0 FIGURE 6-8: Data Ready Behavior. © 2011 Microchip Technology Inc. PHASE = 0 PHASE > 0 MCP3903 DS25048B-page 35 ...
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... MCP3903 6.11 DATA READY PULSE WITH PHASE DELAY To ensure that both channel ADC data from the same pair are present at the same time for SPI read, regard- less of phase delay settings for either or both channels, there are two sets of latches in series with both the data ready and the reading start triggers ...
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... The three bytes of each channel are updated synchronously at a DRCLK rate. The three bytes can be accessed separately if needed, but are refreshed synchronously. The coding is 23-bit + sign two’s complement (see Section 5.5). MCP3903 Description ADC OUTPUT REGISTERS Bits Address Cof ...
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... MCP3903 REGISTER 7-1: CHANNEL REGISTER R-0 R-0 R-0 D23 (MSB) D22 D21 bit 23 R-0 R-0 R-0 D15 D14 D13 bit 15 R-0 R-0 R bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 23:0 24-bit ADC output data of the corresponding channel ...
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... COMP0_CH5 COMP3_CH4 COMP2_CH4 R/W-1 R/W-0 R/W-0 COMP0_CH3 COMP3_CH2 COMP2_CH2 R/W-1 R/W-0 R/W-0 COMP0_CH1 COMP3_CH1 COMP2_CH0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared MCP3903 for this register is R/W-1 R/W-1 COMP1_CH4 COMP0_CH4 bit 16 R/W-1 R/W-1 COMP1_CH2 COMP0_CH2 bit 8 R/W-1 R/W-1 COMP1_CH0 ...
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... MCP3903 7.3 Phase Register TABLE 7-5: PHASE REGISTER Name Bits Address PHASE 24 0x07 The phase register is composed of three bytes: PHASEC<7:0>, PHASEB<7:0>, PHASEA<7:0>. Each byte bit + sign MSB first, two's complement code that represents the amount of delay between each pair of ADCs. The PHASEC byte represents the delay between Channel 4 and Channel 5 (pair C) ...
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... PGA2_CH4 R/W-0 R/W-0 R/W-0 BOOST_ CH3 BOOST_ CH2 PGA2_CH2 R/W-0 R/W-0 R/W-0 BOOST_ CH1 BOOST_ CH0 PGA2_CH0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared MCP3903 R/W-0 R/W-0 PGA1_CH4 PGA0_CH4 bit 16 R/W-0 R/W-0 PGA1_CH2 PGA0_CH2 bit 8 R/W-0 R/W-0 PGA1_CH0 PGA0_CH0 ...
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... MCP3903 7.5 STATUS/COM Register - Status and Communication Register TABLE 7-7: STATUS/COM Register Name Bits Address 0x09 STATUS/COM 24 7.5.1 DATA READY LATENCY - DR_LTY This bit determines if the data ready pulses correspond to settled data or unsettled data from each SINC Unsettled data will provide data ready pulses every DRCLK period ...
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... Data Ready pulses from the lagging ADC channel between the two are output on DRA pin. The lagging ADC channel depends on the phase register and on the OSR. (DEFAULT) bit 5:0 DRSTATUS_CHn: Data Ready Status 1 = Data Not Ready (default Data Ready © 2011 Microchip Technology Inc. MCP3903 DS25048B-page 43 ...
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... MCP3903 7.6 Config Register - Configuration Register TABLE 7-8: CONFIG Register Name Bits Address 0x0A CONFIG 24 REGISTER 7-6: CONFIG REGISTER R/W-0 R/W-0 R/W-0 RESET_CH5 RESET_CH4 RESET_CH3 bit 23 R/W-0 R/W-0 R/W-0 SHUTDOWN_CH1 SHUTDOWN_CH0 DITHER_CH5 DITHER_CH4 SHUTDOWN_ SHUTDOWN_ CH3 CH2 bit 15 R/W-1 R/W-1 R/W-0 ...
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... In the event the full Microchip part number cannot be marked on one line, it will Note: be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2011 Microchip Technology Inc. MCP3903 Example MCP3903 E/ 1124256 Example MCP3903 I/ 1124256 ) e 3 DS25048B-page 45 ...
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... MCP3903 /HDG 3ODVWLF 6KULQN 6PDOO 2XWOLQH 66 ± PP %RG\ >6623@ 1RWH NOTE 1RWHV DS25048B-page © 2011 Microchip Technology Inc. φ L ...
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... Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc. MCP3903 DS25048B-page 47 ...
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... MCP3903 DS25048B-page 48 © 2011 Microchip Technology Inc. ...
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... APPENDIX A: REVISION HISTORY Revision B (July 2011) • Added Section 2.0, Typical Performance Curves, with characterization graphs. Revision A (June 2011) • Original data sheet for the MCP3903 device. © 2011 Microchip Technology Inc. MCP3903 DS25048B-page 51 ...
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... MCP3903 NOTES: DS25048B-page 52 © 2011 Microchip Technology Inc. ...
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... Package Small Shrink Output Package (SSOP-28) © 2011 Microchip Technology Inc. X /XX Examples: a) Package Range b) MCP3903 . MCP3903T-E/SS: Tape and Reel, Six Channel ΔΣ A/D Converter, SSOP-28 package MCP3903T-I/SS: Tape and Reel, Six Channel ΔΣ A/D Converter, SSOP-28 package DS25048B-page 53 ...
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... MCP3903 NOTES: DS25048B-page 54 © 2011 Microchip Technology Inc. ...
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... Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U ...
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