MCP3903-I/SS Microchip Technology, MCP3903-I/SS Datasheet - Page 16

• Manufacturer Part Number: MCP3903-I/SS
• Description: IC AFE 24BIT 64KSPS 28SSOP
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MCP3903-I/SS

• Featured Product: MCP3903 Six Channel ΔΣ A/D Converter
• Number Of Bits: 24
• Number Of Channels: 6
• Power (watts): -
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 3.6 V
• Package / Case: 28-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCP3903
3.10
OSC1/CLKI and OSC2 provide the master clock for the
device. When CLKEXT = 0 (Default), a resonant
crystal or clock source with a similar sinusoidal
waveform must be placed across these pins to ensure
proper operation. The typical clock frequency specified
is 4 MHz. However, the clock frequency can be 1 MHz
to 5 MHz without disturbing ADC accuracy. With the
current boost circuit enabled, the master clock can be
used up to 8.192 MHz without disturbing ADC
accuracy. Appropriate load capacitance should be
connected to these pins for proper operation.
3.11
This pin is the SPI Chip Select that enables the serial
communication.
communication can take place. A chip select falling
edge initiates the serial communication and a chip
select rising edge terminates the communication. No
communication can take place even when CS is low
and when RESET is low.
This input is Schmitt-triggered.
DS25048B-page 16
Note:
Oscillator And Master Clock Input
Pins (OSC1/CLKI, OSC2)
CS (Chip Select)
When CLKEXT = 1, the crystal oscillator
is disabled, as well as the OSC2 input.
The OSC1 becomes the master clock
input CLKI, direct path for an external
clock source, for example a clock source
generated by an MCU.
When
this
pin
is
high,
no
3.12
This is the serial clock pin for SPI communication. Data
is clocked into the device on the RISING edge of SCK.
Data is clocked out of the device on the FALLING edge
of SCK. The MCP3903 interface is compatible with
both SPI 0,0 and 1,1 modes. The maximum clock
speed specified is 10 MHz. This input is Schmitt
triggered.
3.13
This is the SPI data output pin. Data is clocked out of
the device on the FALLING edge of SCK. This pin stays
at high impedance during the control byte. It also stays
at high impedance during the whole communication for
write commands and when the CS pin is high or when
the RESET pin is low. This pin is active only when a
read command is processed. Each read is processed
by a packet of 24 bits (size of each register), except on
the ADC output registers when WIDTH=0.
3.14
This is the SPI data input pin. Data is clocked into the
device on the RISING edge of SCK. When CS is low,
this pin is used to communicate with a series of 8-bit
commands. The interface is half-duplex (inputs and
outputs do not happen at the same time). Each
communication starts with a chip select falling edge
followed by an 8-bit control byte entered through the
SDI pin. Each write is processed by packets of 24 bits
(size of each register). Each command is either a Read
or a Write command. Toggling SDI during a Read
command has no effect. This input is Schmitt-triggered.
SCK (Serial Data Clock)
SDO (Serial Data Output)
SDI (Serial Data Input)
© 2011 Microchip Technology Inc.