MCP3903-I/SS Microchip Technology, MCP3903-I/SS Datasheet - Page 17

IC AFE 24BIT 64KSPS 28SSOP

MCP3903-I/SS

Manufacturer Part Number
MCP3903-I/SS
Description
IC AFE 24BIT 64KSPS 28SSOP
Manufacturer
Microchip Technology
Series
-r
Datasheet

Specifications of MCP3903-I/SS

Featured Product
MCP3903 Six Channel ΔΣ A/D Converter
Number Of Bits
24
Number Of Channels
6
Power (watts)
-
Voltage - Supply, Analog
4.5 V ~ 5.5 V
Voltage - Supply, Digital
2.7 V ~ 3.6 V
Package / Case
28-SSOP (0.209", 5.30mm Width)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Quantity
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Part Number:
MCP3903-I/SS
Manufacturer:
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Quantity:
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Part Number:
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Manufacturer:
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4.0
This section defines the terms and formulas used
throughout this data sheet. The following terms are
defined:
MCLK - Master Clock
AMCLK - Analog Master Clock
DMCLK - Digital Master Clock
DRCLK - Data Rate Clock
OSR - Oversampling Ratio
Offset Error
Gain Error
Integral Non-Linearity Error
Signal-To-Noise Ratio (SNR)
Signal-To-Noise Ratio And Distortion (SINAD)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
MCP3903 Delta-Sigma Architecture
Idle Tones
Dithering
Crosstalk
PSRR
CMRR
ADC Reset Mode
Hard Reset Mode (RESET = 0)
ADC Shutdown Mode
Full Shutdown Mode
4.1
This is the fastest clock present in the device. This is
the frequency of the crystal placed at the OSC1/OSC2
inputs when CLKEXT = 0 or the frequency of the clock
input at the OSC1/CLKI when CLKEXT = 1.
© 2011 Microchip Technology Inc.
TERMINOLOGY AND
FORMULAS
MCLK - Master Clock
4.2
This is the clock frequency that is present on the analog
portion of the device, after prescaling has occurred via
the CONFIG PRESCALE<1:0> register bits. The
analog portion includes the PGAs and the two
sigma-delta modulators.
EQUATION 4-1:
TABLE 4-1:
4.3
This is the clock frequency that is present on the digital
portion of the device, after prescaling and division by 4.
This is also the sampling frequency, that is the rate at
which the modulator outputs are refreshed. Each
period of this clock corresponds to one sample and one
modulator output.
EQUATION 4-2:
4.4
This is the output data rate i.e. the rate at which the
ADCs output new data. Each new data is signaled by a
data ready pulse on the DR pin.
This data rate is depending on the OSR and the
prescaler with the following formula:
EQUATION 4-3:
DRCLK
PRE<1:0>
0
0
1
1
Config
DMCLK
AMCLK - Analog Master Clock
DMCLK - Digital Master Clock
DRCLK - Data Rate Clock
=
DMCLK
--------------------- -
0
1
0
1
OSR
AMCLK
=
MCP3903 OVERSAMPLING
RATIO SETTINGS
AMCLK
-------------------- -
=
AMCLK = MCLK/ 1 (default)
AMCLK
---------------------
4
4
×
=
Analog Master Clock
OSR
AMCLK = MCLK/ 2
AMCLK = MCLK/ 4
AMCLK = MCLK/ 8
------------------------------ -
PRESCALE
=
MCLK
MCP3903
=
--------------------------------------- -
4 PRESCALE
Prescale
×
---------------------------------------------------------- -
4
×
MCLK
OSR
DS25048B-page 17
MCLK
×
PRESCALE

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