MCP3903-I/SS Microchip Technology, MCP3903-I/SS Datasheet - Page 18

• Manufacturer Part Number: MCP3903-I/SS
• Description: IC AFE 24BIT 64KSPS 28SSOP
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MCP3903-I/SS

• Featured Product: MCP3903 Six Channel ΔΣ A/D Converter
• Number Of Bits: 24
• Number Of Channels: 6
• Power (watts): -
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 3.6 V
• Package / Case: 28-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCP3903
Since this is the output data rate, and since the
decimation filter is a SINC (or notch) filter, there is a
notch in the filter transfer function at each integer
multiple of this rate.
TABLE 4-2:
4.5
The ratio of the sampling frequency to the output data
rate is OSR = DMCLK/DRCLK. The default OSR is 64,
or with MCLK = 4 MHz, PRESCALE = 1, AMCLK = 4
MHz, f
in the CONFIG1 register are used to change the
oversampling ratio (OSR).
TABLE 4-3:
DS25048B-page 18
Note:
OSR<1:0>
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
CONFIG
<1:0>
PRE
S
= 1 MHz, f
OSR - Oversampling Ratio
For OSR = 32 and 64, DITHER = 0. For OSR = 128 and 256, DITHER = 1.
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
0
1
DEVICE DATA RATES IN FUNCTION OF MCLK, OSR, AND PRESCALE
MCP3903 OVERSAMPLING
RATIO SETTINGS
D
OSR <1:0>
= 15.625 ksps. The following bits
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
OVER SAMPLING RATIO
64 (DEFAULT)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
(OSR)
128
256
32
OSR
256
128
256
128
256
128
256
128
64
32
64
32
64
32
64
32
AMCLK
MCLK/8
MCLK/8
MCLK/8
MCLK/8
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/2
MCLK/2
MCLK/2
MCLK/2
MCLK
MCLK
MCLK
MCLK
The following table describes the various combinations
of OSR and PRESCALE and their associated AMCLK,
DMCLK and DRCLK rates.
4.6
This is the error induced by the ADC when the inputs
are shorted together (V
incorporates both PGA and ADC offset contributions.
This error varies with PGA and OSR settings. The
offset is different on each channel and varies from chip
to chip. This offset error can easily be calibrated out by
a MCU with a subtraction. The offset is specified in mV.
The offset on the MCP3903 has a low temperature
coefficient, see
Curves”.
4.7
This is the error induced by the ADC on the slope of the
transfer function. It is the deviation expressed in %
compared to the ideal transfer function defined by
Equation
and ADC gain error contributions, but not the V
contribution (it is measured with an external V
error varies with PGA and OSR settings.
The gain error on the MCP3903 has a low temperature
coefficient. See the typical performance curves for
more information.
MCLK/32
MCLK/32
MCLK/32
MCLK/32
MCLK/16
MCLK/16
MCLK/16
MCLK/16
DMCLK
MCLK/8
MCLK/8
MCLK/8
MCLK/8
MCLK/4
MCLK/4
MCLK/4
MCLK/4
Offset Error
Gain Error
5-3. The specification incorporates both PGA
Section 2.0 “Typical Performance
MCLK/8192
MCLK/4096
MCLK/2048
MCLK/1024
MCLK/4096
MCLK/2048
MCLK/1024
MCLK/2048
MCLK/1024
MCLK/1024
MCLK/512
MCLK/512
MCLK/256
MCLK/512
MCLK/256
MCLK/128
DRCLK
© 2011 Microchip Technology Inc.
IN
= 0V). The specification
DRCLK
0.4882
7.8125
7.8125
15.625
7.8125
15.625
(ksps)
0.976
0.976
31.25
1.95
1.95
1.95
3.9
3.9
3.9
3.9
REF
).This
REF