MCP3903-I/SS Microchip Technology, MCP3903-I/SS Datasheet - Page 28

• Manufacturer Part Number: MCP3903-I/SS
• Description: IC AFE 24BIT 64KSPS 28SSOP
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MCP3903-I/SS

• Featured Product: MCP3903 Six Channel ΔΣ A/D Converter
• Number Of Bits: 24
• Number Of Channels: 6
• Power (watts): -
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 3.6 V
• Package / Case: 28-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCP3903
5.7
The MCP3903 contains an internal POR circuit that
monitors analog supply voltage AV
The typical threshold for a power-up event detection is
4.2V ±5%. The POR circuit has a built-in hysteresis for
improved transient spikes immunity that has a typical
value of 200 mV. Proper decoupling capacitors (0.1 µF
ceramic and 10 µF tantalum) should be mounted as
close as possible to the AV
transient immunity.
Figure 5-3
power-up and a power-down event, in typical
conditions. All internal DC biases are not settled until at
least 50 µs after system POR. Any data ready pulses
during this time after system reset should be ignored.
After POR, data ready pulses are present at the pin
with all the default conditions in the configuration regis-
ters.
Both AV
Since AV
it is highly recommended to power up DV
power-up sequence. If AV
highly recommended to keep the RESET pin low during
the whole power-up sequence.
FIGURE 5-3:
DS25048B-page 28
DEVICE
MODE
AV
4.2V
5V
4V
0V
DD
DD
Power-on Reset
DD
and DV
is the only power supply that is monitored,
illustrates the different conditions at
RESET
50 µs
DD
t
POR
power supplies are independent.
Power-on Reset Operation.
OPERATION
PROPER
DD
DD
is powered up first, it is
pin, providing additional
DD
during operation.
RESET
DD
first as a
Time
5.8
When the RESET pin is low, both ADCs will be in Reset
and output code 0x0000h. The RESET pin performs a
hard reset (DC biases still on, part ready to convert)
and clears all charges contained in the sigma delta
modulators. The comparator outputs are 0011 for each
ADC.
The SINC filters are all reset, as well as their double
output buffers. This pin is independent of the serial
interface. It brings the CONFIG registers to the default
state. When RESET is low, any write with the SPI
interface will be disabled and will have no effect. All
output pins (SDO, DR, MDAT0/1) are high impedance,
and no clock is propagated through the chip.
5.9
The MCP3903 incorporates a phase delay generator
which ensures that the six ADCs are converting the
inputs with a fixed delay between them. The six ADCs
are synchronously sampling but the averaging of
modulator outputs is delayed so that the SINC filter
outputs (thus the ADC outputs) show a fixed phase
delay, as determined by the PHASE register setting.
The phase register is composed of three bytes:
PHASEC<7:0>, PHASEB<7:0>, PHASEA<7:0>. Each
byte is a 7 bit + sign MSB first, two's complement code
that represents the amount of delay between each pair
of ADCs. The PHASEC byte represents the delay
between Channel 4 and channel 5 (pair C). The
PHASEB byte represents the delay between Channel 2
and channel 3 (pair B). The PHASEA byte represents
the delay between Channel 0 and channel 1 (pair A).
The reference channel is the odd channel (channel 1/
3/5). When PHASEn<7:0> is positive, Channel 0/2/4 is
lagging versus channel 1/3/5 otherwise it is leading.
The amount of delay between two ADC conversions is
given by the following formula:
EQUATION 5-5:
The timing resolution of the phase delay is 1/DMCLK or
1 µs in the default configuration with MCLK = 4 MHz.
The data ready signals are affected by the phase delay
settings. Typically, the time difference between the data
ready pulses of channel 0 and channel 1 is equal to the
phase delay setting.
Note:
RESET Effect On Delta Sigma
Modulator/SINC Filter
Phase Delay Block
Delay
A detailed explanation of the Data Ready
pins (DRn) with phase delay is present in
Section 6.10
(DRn)”.
=
Phase Register Code
------------------------------------------------- -
© 2011 Microchip Technology Inc.
DMCLK
“Data
Ready
Pulses