MCP3903-I/SS Microchip Technology, MCP3903-I/SS Datasheet - Page 33

• Manufacturer Part Number: MCP3903-I/SS
• Description: IC AFE 24BIT 64KSPS 28SSOP
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MCP3903-I/SS

• Featured Product: MCP3903 Six Channel ΔΣ A/D Converter
• Number Of Bits: 24
• Number Of Channels: 6
• Power (watts): -
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 3.6 V
• Package / Case: 28-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.7.1
All ADCs are powered up with their default
configurations, and begin to output data ready pulses
immediately (RESET<5:0> and SHUTDOWN<5:0>
bits are off by default). The default output codes for
both ADCs are all zeros.The default modulator output
for both ADCs is 0011 (corresponding to a theoretical
zero voltage at the inputs). The default phase is zero
between the two channels. It is recommended to enter
into ADC reset mode for both ADCs just after power-up
because the desired MCP3903 register configuration
may not be the default one and in this case, the ADC
would output undesired data. Within the ADC reset
mode (RESET<5:0>=111111), the user can configure
the whole part with a single communication. The write
commands automatically increment the address so the
user can start writing the PHASE register and finish
with the CONFIG register in only one communication
(see Figure 6-6). The RESET<5:0> bits are in the
CONFIG register to allow it to exit soft reset mode and
have the whole part configured and ready to run in only
one command.
TABLE 6-1:
The following internal registers are defined as types:
TABLE 6-2:
6.8
Immediately after the following actions, the ADCs are
reset and automatically restarted in order to provide
proper operations:
© 2011 Microchip Technology Inc.
Pair A, CHANNEL 0/1
Pair B, CHANNEL 2/3
Pair C, CHANNEL 4/5
MOD, PHASE, GAIN
STATUS, CONFIG
ADC DATA
CONTROL
TYPE
1: Change in phase register
2: Change in the OSR setting
3: Change in the PRESCALER setting
4: Overwrite of identical PHASE register
5: Change in EXTCLK bit in the CONFIG
GROUP
Situations that Reset ADC Data
CONTINUOUS READ
value
register modifying internal oscillator state.
REGISTER GROUPS
REGISTER TYPES
ADDRESSES
0x06 - 0x0A
0x00 - 0x05
ADDRESSES
0x09 - 0x0A
0x00 - 0x01
0x02 - 0x03
0x04 - 0x05
0x06 - 0x08
After these temporary resets, the ADCs go back to
normal operation with no need for an additional
command. These are also the settings where the DR
position is affected. The phase register can be used to
soft reset the ADC without using the RESET bits in the
configuration register.
6.9
Since the AMCLK range can go up to 5 MHz, the
MCP3903 is able to accommodate 256 output samples
per line cycles with line frequencies up to 76.2Hz at
OSR=64.
.
TABLE 6-1:
Figure 6-7 illustrates operating the part in this manner
(timings not to scale, functional description only).
All channels are continuously converting during normal
operation of the device except when it is in Sleep Mode
by using the RESET bit, or if RESET is low. The
following figure represents the clocking scheme and
how
OSR<1:0> bits registers is used to modify the clock
prescale and oversampling ratio.
For example, if a data ready pulse occurs while ADC
data (a) is being transmitted on SPI, this data will not
be corrupt in any way. After CS is toggled low to begin
another transmission, the next data (b) would be
present in the output buffer ready for transmission.
SAMPLES
OUTPUT
CYCLE
/ LINE
128
256
64
the
Line Cycle Sampling Options
CONFIG
5.76 ksps
11.5 ksps
2.8 ksps
F
F
D
LINE
MCLK FREQUENCIES FOR
LINE SAMPLING
OSR = 64
= 45 HZ
737.28 kHz
1.475 MHz
2.949 MHz
PRESCALE<1:0>
MCLK
MCP3903
16.7 ksps
4.2 ksps
8.4 ksps
DS25048B-page 33
F
F
D
LINE
OSR = 64
= 65 HZ
1.075 MHz
bits
2.15 MHz
4.3 MHz
MCLK
and