STA333W13TR STMicroelectronics, STA333W13TR Datasheet
STA333W13TR
Specifications of STA333W13TR
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STA333W13TR Summary of contents
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... Advanced AM interference frequency switching and noise suppression modes Thermal-overload and short-circuit protection embedded Video application: 576 * f S Table 1. Device summary Order code STA333W STA333W13TR January 2010 2-channel high-efficiency digital audio system Applications LCD DVD Cradle Digital speaker Wireless-speaker cradle Description The STA333W is an integrated circuit comprising ...
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Contents Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STA333W 5.4.1 5.4.2 5.4.3 5.4.4 6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STA333W List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STA333W 1 Block diagram Figure 1. Block diagram interface Volume control PLL Digital DSP Protection current/thermal Power control DDX Regulators Doc ID 13365 Rev 2 Block diagram Channel 1A Channel 1B Logic Channel 2A ...
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Pin description 2 Pin description 2.1 Pin out Figure 2. Pin connection (package top view) TEST_MODE GND_REG 2.2 Pin list Table 2. Pin description Number Type 1 PWR I PWR ...
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STA333W Table 2. Pin description (continued) Number Type PWR 12 PWR PWR 15 PWR PWR 22 PWR PWR 25 I ...
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Pin description 2.3 Thermal data Table 3. Thermal data Symbol R Thermal resistance junction to case (thermal pad) Th(j-case) T Thermal-shutdown junction temperature sd T Thermal-warning temperature w T Thermal-shutdown hysteresis hsd 10/49 Parameter Doc ID 13365 Rev 2 STA333W ...
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STA333W 3 Electrical specification 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings Symbol V Analog supply voltage (pins VCCx Digital supply voltage (pins VDD_DIG Logic input interface L T Operating junction temperature op T Storage ...
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Electrical specification 3.3 Electrical specifications - digital section Table 6. Electrical characteristics for digital section Symbol I Input current, no pull- pull-down resistor Low-level input voltage il V High-level input voltage ih V Low-level output ...
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STA333W Table 7. Electrical specifications for power section (continued) Symbol V Supply voltage CC Supply current from V power down I VCC Supply current from V operation Supply current for DDX processing (reference only) I VDD_DIG Supply current in standby ...
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Electrical specification 3.5 Power-on/off sequences The power-on/off sequences shown in on and turn off. Figure 3. Power-on sequence VCC VCC VCC VDD_Dig VDD_Dig VDD_DIG XTI XTI XTI Reset Reset RESET PWRDN PWRDN PWRDN Bit EAPD Soft EAPD Soft EAPD Register ...
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STA333W 3.6 Testing Figure 5. Test circuit Duty cycle = 50% Figure 6. Current dead-time test circuit Duty cycle=A DTin(A) INA Low current dead time = MAX(DTr,DTf) +Vcc M58 OUTxY INxY M57 gnd High Current Dead time for Bridge application ...
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Functional description 4 Functional description 4.1 Functional pins 4.1.1 Power-down function Pin PWRDN (23) is used to power down the STA333W. PWRDN = 0 (0 V): power-down state. PWRND = During the power-down sequence the output begins ...
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STA333W 4.2 Serial audio interface description 4.2.1 Serial audio interface protocols The STA333W serial audio input was designed to interface with standard digital audio components and to accept serial data formats. The STA333W always acts as a slave when receiving ...
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I C bus specification bus specification The STA333W supports the I defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The ...
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STA333W 5.3 Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA333W acknowledges this and then waits for the byte of internal address. After receiving the internal byte ...
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I C bus specification 5.4.4 Random address multi-byte read The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA333W. The master acknowledges each data byte read and then ...
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STA333W 6 Register description Table 8. Register summary Addr Name 0x00 CONFA 0x01 CONFB 0x02 CONFC 0x03 CONFD 0x04 CONFE 0x05 CONFF 0x06 MUTE 0x07 MVOL 0x08 C1VOL 0x09 C2VOL 0x0C AUTO 0x0E C1CFG 0x0F C2CFG 0x27 MPCC1 0x28 MPCC2 ...
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Register description 6.1 Configuration registers (addr 0x00 to 0x05) 6.1.1 Configuration register A (addr 0x00 FDRB TWAB 0 1 Master clock select Table 9. Master clock select Bit R/W 0 R/W 1 R/W 2 R/W The STA333W supports ...
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STA333W Interpolation ratio select Table 11. Interpolation ratio select Bit R/W 4:3 R/W The STA333W has variable interpolation (oversampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 2 times or ...
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Register description Thermal warning adjustment bypass Table 14. Thermal warning adjustment Bit R/W 6 R/W The on-chip STA333W power output block provides feedback to the digital controller using inputs to the power control block. The TWARN input is used to ...
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STA333W Serial audio input interface format Table 16. Serial audio input interface format Bit R/W 0 R/W 1 R/W 2 R/W 3 R/W Serial data interface The STA333W audio serial input interfaces with standard digital audio components and accepts a ...
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Register description Table 18. Support serial audio input formats for MSB first (SAIFB = 0) (continued) 64 Supported serial audio input formats for LSB-First (SAIFB = 1) Table 19. BICKI 32 48 48* f ...
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STA333W Channel input mapping Table 20. Channel input mapping Bit R/W 6 R/W 7 R/W Each channel received via I channel input mapping registers. This allows for flexibility in processing. The default settings of these registers map each I 6.1.3 ...
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Register description Overcurrent warning detect adjustment bypass Table 23. Overcurrent warning detect adjustment bypass Bit R/W 7 R/W The status bit OCWARN is used to warn of an overcurrent condition. When OCWARN is asserted (set to 0), the power control ...
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STA333W Max power correction Table 26. Max power correction Bit R/W 1 R/W Setting the MPC bit turns on special processing that corrects the STA333W power device at high power. This mode lowers the THD full DDX system ...
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Register description Zero-crossing volume enable Table 31. Zero-crossing volume enable Bit R/W 6 R/W The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks will be audible. Soft volume update enable Table 32. Zero-crossing ...
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STA333W LRCK double trigger protection Table 35. LRCK double trigger protection Bit R/W 4 R/W Actively prevents double trigger of LRCLK. Auto EAPD on clock loss Table 36. Auto EAPD on clock loss Bit R/W 5 R/W When active will ...
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Register description 6.2 Volume control registers (addr 0x06 to 0x09) 6.2.1 Mute/line output configuration register (addr 0x06 Master mute Table 39. Master mute Bit R/W 0 R/W Channel mute Table 40. Channel mute Bit R/W 1 ...
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STA333W 6.2.2 Master volume register (addr 0x07 MV7 MV6 1 1 6.2.3 Channel volume (addr 0x08, 0x09 C1V7 C1V6 C2V7 C2V6 0 1 Volume setting The volume structure of the STA333W consists ...
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Register description Table 42. Channel volume as a function of CxV 00000000 (0x00) 00000001 (0x01) 00000010 (0x02) … 01011111 (0x5F) 01100000 (0x60) 01100001 (0x61) … 11010111 (0xD7) 11011000 (0xD8) 11011001 (0xD9) 11011010 (0xDA) … 11101100 (0xEC) 11101101 (0xED) … 11111111 ...
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STA333W Table 44. Automodes™ AM switching frequency selection 010 011 100 101 110 6.4 Channel configuration registers (addr 0x0E, 0x0F Volume bypass Each channel contains an individual channel volume bypass ...
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Register description 6.6 Variable distortion compensation registers (addr 0x29, 0x2A DCC15 DCC14 DCC7 DCC6 0 0 DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient is used in place of ...
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STA333W Table 45. Status bits description (continued) Bit R 6.9 Reserved registers (addr 0x2E, 0x2F, 0x30, 0x31) These registers are not to be used. 6.10 Postscale registers (addr ...
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Register description 6.11 Output limit register (addr 0x34) 6.11.1 Thermal and overcurrent warning output limit register D7 D6 OLIM7 OLIM6 0 The STA333W provides a simple mechanism for reacting to a thermal or overcurrent warning in the power device. When ...
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STA333W 7 Applications information 7.1 Applications scheme for power supplies Figure 11 below shows a typical applications scheme for STA333W. Special care has to be taken with regard to the power supplies when laying out the PCB. In particular the ...
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Applications information Figure 12. PLL filter circuit 7.3 Typical output configuration Figure 13 below shows a typical output configuration used for BTL stereo mode. Figure 13. Output configuration for stereo BTL mode OUT1A OUT1A OUT1A OUT1B OUT1B OUT1B OUT2A OUT2A ...
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STA333W 8 Characterization data The following characterizations were made with R stated. Figure 14. Output power vs. supply voltage (THD = 1 Figure 15. ...
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Characterization data Figure 16. FFT -60 dBfs (V +10 + -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 - -70 - -80 - -90 -90 -100 -100 ...
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STA333W Figure 18. FFT 0 dBfs (V +10 + -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 - -70 - -80 - -90 -90 -100 -100 -110 ...
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Package thermal characteristics 9 Package thermal characteristics A thermal resistance of 25 °C/W can be achieved by mounting the device on a PCB which has two copper ground areas and 16 vias (see Given that ...
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STA333W 10 Package mechanical data The STA333W comes in a 36-pin PowerSSO package with exposed pad down (EPD). Figure 23 below shows the package outline and Figure 23. PowerSSO-36 EPD outline drawing Table 47 gives the dimensions. Doc ID 13365 ...
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Package mechanical data Table 47. PowerSSO-36 EPD dimensions Symbol Min A 2.15 A2 2.15 a1 0.00 b 0.18 c 0.23 D 10. 10. 0.60 ...
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... STA333W 11 Trademarks and other acknowledgements DDX is a registered trademark of Apogee Technology Inc. Automodes is a trademark of Apogee Technology Inc. ECOPACK is a registered trademark of STMicroelectronics. Sound Terminal is a trademark of STMicroelectronics. Trademarks and other acknowledgements Doc ID 13365 Rev 2 47/49 ...
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Revision history 12 Revision history Table 48. Document revision history Date 25-May-2007 21-Jan-2010 48/49 Revision 1 Initial release. Updated features for operating voltage range, digital gain increments and maximum power control Updated description Updated electrical specifications page 11 Added Section ...
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... STA333W Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...