AT89C51ID2-SLSIM Atmel, AT89C51ID2-SLSIM Datasheet
AT89C51ID2-SLSIM
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AT89C51ID2-SLSIM Summary of contents
Page 1
... Packages: PLCC44, VQFP44 Description AT89C51ID2 is a high performance CMOS Flash version of the 80C51 CMOS single chip 8-bit microcontroller. It contains a 64 Kbytes Flash memory block for program and for data. The 64 Kbytes Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software ...
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... AT89C51ID2 2 The AT89C51ID2 retains all features of the Atmel 80C52 with 256 bytes of internal RAM, a 10-source 4-level interrupt controller and three timer/counters. In addition, the AT89C51ID2 has a Programmable Counter Array, an XRAM of 1792 bytes, a Hardware Watchdog Timer, SPI and Keyboard, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a speed improvement mechanism (X2 mode) ...
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... CPU Parallel I/O Ports & Timer 0 INT External Bus Timer 1 Ctrl Port 2 Port 0 Port 1 (2) (2) (2) (2) (1): Alternate function of Port 1 (2): Alternate function of Port 3 (3): Alternate function of Port I2 AT89C51ID2 (1) (1) (1) (1) (1) Watch XRAM Dog PCA Keyboard Timer2 1792 x 8 POR PFD ...
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... SFR Mapping 4289C–8051–11/05 The Special Function Registers (SFRs) of the AT89C51ID2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3, PI2 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • ...
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... Add Name IEN0 A8h Interrupt Enable Control 0 IEN1 B1h Interrupt Enable Control 1 IPH0 B7h Interrupt Priority Control High 0 IPL0 B8h Interrupt Priority Control Low 0 IPH1 B3h Interrupt Priority Control High 1 IPL1 B2h Interrupt Priority Control Low 1 AT89C51ID2 RS1 SMOD1 SMOD0 - POF - - ...
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... FPL3 FPL2 FPL1 FPL0 TF1 TR1 TF0 TR0 GATE1 C/T1# M11 M01 - - - - TF2 EXF2 RCLK TCLK - - - - AT89C51ID2 FPS FMOD1 FMOD0 FBUSY IE1 IT1 IE0 IT0 GATE0 C/T0# M10 M00 - WTO2 WTO1 WTO0 EXEN2 TR2 C/T2# CP/RL2 T2OE DCEN 6 ...
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... Slave Address BDRCON 9Bh Baud Rate Control BRL 9Ah Baud Rate Reload Table 10. SPI Controller SFRs Mnemonic Add Name SPCON C3h SPI Control SPSTA C4h SPI Status SPDAT C5h SPI Data AT89C51ID2 CCF4 CIDL WDTE - - ECOM0 CAPP0 CAPN0 ECOM1 CAPP1 CAPN1 ...
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... SSC2 SSC1 SSD7 SSD6 SSD5 SSD4 SSA7 SSA6 SSA5 SSA4 KBLS7 KBLS6 KBLS5 KBLS4 KBE7 KBE6 KBE5 KBE4 KBF7 KBF6 KBF5 KBF4 AT89C51ID2 SSI SSAA SSCR1 SSCR0 SSC0 SSD3 SSD2 SSD1 SSD0 SSA3 SSA2 SSA1 SSGC KBLS3 KBLS2 KBLS1 KBLS0 KBE3 ...
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... TCON TMOD 88h 0000 0000 0000 0000 P0 SP 80h 0000 0111 1111 1111 0/8 1/9 AT89C51ID2 9 Table below shows all SFRs with their address and their reset value. Non Bit addressable 2/A 3/B 4/C CCAP0H CCAP1H CCAP2H XXXX XXXX XXXX XXXX ...
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... P3.1/TxD 13 PLCC44 P3.2/INT0 14 P3.3/INT1 15 P3.4/T0 16 P3.5/ P1.5/CEX2/MISO P1.6/CEX3/SCK P1.7/CEX4/MOSI P3.0/RxD PI2.1/SDA P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 AT89C51ID2 39 P0.4/AD4 38 P0.5/AD5 37 P0.6/AD6 36 P0.7/AD7 PI2.0/SCL 33 ALE/PROG 32 PSEN 31 P2.7/A15 30 P2.6/A14 29 P2.5/A13 RST 4 5 AT89C51ID2 6 VQFP44 1 P0.4/AD4 32 P0.5/AD5 31 P0.6/AD6 30 P0.7/AD7 PI2.0/SCL 27 ALE/PROG 26 PSEN 25 P2.7/A15 24 P2.6/A14 23 P2.5/A13 10 ...
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... As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1 also receives the low-order address byte during memory programming and verification. Alternate functions for AT89C51ID2 Port 1 include: I/O P1.0: Input/Output I/O T2 (P1 ...
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... Port 5 pins that are externally pulled low will source current because of the internal pull-ups. Port I2: Port open drain. It can be used as inputs (must be polarized to Vcc with external resistor to prevent any parasitic current consumption). I/O SCL (PI2.0): 2-wire Serial Clock SCL output the serial clock to slave peripherals SCL input the serial clock from master AT89C51ID2 12 ...
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... ALE/PROG 33 27 PSEN AT89C51ID2 13 Type Name and Function SDA (PI2.1): 2-wire Serial Data I/O SDA is the bidirectional 2-wire data line Reset: A high on this pin for two machine cycles while the oscillator is running, resets the I device. An internal diffused resistor to V capacitor to V ...
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... Cleared, CPU and peripherals connected to OSCB 0 CKS Set, CPU and peripherals connected to OSCA Programmed by hardware after a Power-up regarding Hardware Security Byte (HSB).HSB.OSC (Default setting, OSCA selected) Reset Value = 0000 000’HSB.OSC’b (see Hardware Security Byte (HSB)) Not bit addressable AT89C51ID2 ...
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... AT89C51ID2 15 Table 17. OSCCON Register (for AT8xC51Ix2 only) OSCCON- Oscillator Control Register (86h Bit Bit Number Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved Sub Clock Timer0 Cleared by software to select T0 pin 2 SCLKT0 Set by software to select T0 Sub Clock Cleared by hardware after a Power Up OscB enable bit ...
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... Set by software for general purpose usage. Power-Down mode bit 1 PD Cleared by hardware when reset occurs. Set to enter power-down mode. Idle mode bit 0 IDL Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. Reset Value = 00X1 0000b Not bit addressable AT89C51ID2 POF GF1 GF0 IDL 16 ...
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... Diagram Figure 2. Functional Oscillator Block Diagram PwdOscA FOSCA XtalA1 OscA XtalA2 OscAEn OSCCON PwdOscB XtalB1 XtalB2 Operating Modes Reset Functional Modes Normal Modes AT89C51ID2 17 Reload Reset CKRL 1 8-bit :2 0 Prescaler-Divider X2 CKCON0 CKRL=0xFF? OscB OscBEn OSCCON A hardware RESET puts the Clock generator in the following state: The selected oscillator depends on OSC bit in Hardware Security Byte (HSB) ...
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... AT89C51ID2 CKS Selected Mode Comment NORMAL MODE Default mode after power- OscB stopped Warm Reset NORMAL MODE Default mode after power- OscB running Warm Reset + OscB running NORMAL MODE 0 OscB running and selected B, OscA stopped NORMAL MODE OscB running and selected + ...
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... Design Considerations Oscillators Control Prescaler Divider AT89C51ID2 19 Table 20. Overview (Continued) PCON.1 PCON.0 OscBEn OscAEn • PwdOscA and PwdOscB signals are generated in the Clock generator and used to control the hard blocks of oscillators A and B. • PwdOscA =’1’ stops OscA • PwdOscB =’1’ stops OscB • ...
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... The SCLKT0 bit in OSCCON register allows to select Timer 0 Subsidiary clock. SCLKT0 = 0: Timer 0 uses the standard T0 pin as clock input (Standard mode) SCLKT0 = 1: Timer 0 uses the special Sub Clock as clock input, this feature can be use as periodic interrupt for time clock. AT89C51ID2 F OSCA --------------------------------------------- - = × ...
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... ALE disabling • Enhanced features on the UART and the timer 2 The AT89C51ID2 core needs only 6 clock periods per machine cycle. This feature called ‘X2’ provides the following advantages: • Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. ...
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... Figure 4. Mode Switching Waveforms XTAL1 XTAL1:2 X2 bit CPU clock STD Mode AT89C51ID2 22 F OSC X2 Mode The X2 bit in the CKCON0 register (see Table 21) allows a switch from 12 clock periods per instruction to 6 clock periods and vice versa. At reset, the speed is set according to X2 bit of Hardware Security Byte (HSB). By default, Standard mode is active. Setting the X2 bit activates the X2 feature (X2 mode) ...
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... Set to select 6clock periods per machine cycle (X2 mode) and enable the individual peripherals’X2’ bits. Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), Default setting cleared. Reset Value = 0000 000’HSB. X2’b (See “Hardware Security Byte”) Not bit addressable AT89C51ID2 SIX2 T2X2 T1X2 T0X2 ...
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... AT89C51ID2 24 Table 22. CKCON1 Register CKCON1 - Clock Control Register (AFh Bit Bit Number Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved 2 - Reserved 1 - Reserved SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). 0 SPIX2 Clear to select 6 clock periods per peripheral clock cycle. ...
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... There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1.0 (see Table 23) that allows the program code to switch between them (Refer to Figure 5). 0 DPS DPTR1 DPH(83H) DPL(82H) AT89C51ID2 External Data Memory DPTR0 25 ...
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... AT89C51ID2 26 Table 23. AUXR1 register AUXR1- Auxiliary Register 1(0A2h ENBOOT Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Enable Boot Flash Cleared to disable boot ROM ...
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... DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state. AT89C51ID2 27 ...
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... AT89C51ID2 devices have expanded RAM in external data space configurable up to 1792bytes (see Table 24.). The AT89C51ID2 has internal data memory that is mapped into four separate segments. The four segments are: 1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable ...
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... AT89C51ID2 29 useful if external peripherals are mapped at addresses already used by the internal XRAM. • With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0 the selected bank or DPTR. An access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H rather than external memory ...
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... ALE Output bit Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1 mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is used. Reset Value = XX00 10’HSB. XRAM’0b Not bit addressable AT89C51ID2 XRS2 XRS1 XRS0 0 256 bytes ...
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... The Reset input can be used to force a reset pulse longer than the internal reset con- trolled by the Power Monitor. RST input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to V value and input characteristics are discussed in the Section “DC Characteristics” of the AT89C51ID2 datasheet. Figure 8. Reset Circuitry and Power-On Reset RST VSS a ...
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... RST pin. In order to properly propagate this pulse to the rest of the application in case of external capacitor or power-supply supervisor circuit kΩ resistor must be added as shown Figure 9. Figure 9. Recommended Reset Output Schematic VDD + RST VDD 1K RST VSS AT89C51ID2 To other on-board circuitry 4289C–8051–11/05 ...
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... This is achieved by applying an internal reset to them. By generating the Reset the Power Monitor insures a correct start up when AT89C51ID2 is powered up. In order to startup and maintain the microcontroller in correct operating mode stabilized in the V ...
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... Figure 11. Power Fail Detect Vcc Reset Vcc AT89C51ID2 34 The Power fail detect monitor the supply generated by the voltage regulator and gener- ate a reset if this supply falls below a safety threshold as illustrated in the Figure 11 below. When the power is applied, the Power Monitor immediately asserts a reset. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL clock input ...
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... Timer 2 Auto-Reload Mode 4289C–8051–11/05 The Timer 2 in the AT89C51ID2 is the standard C52 Timer 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded controlled by T2CON (Table 25) and T2MOD (Table 26) registers. Timer 2 operation is similar to Timer 0 and Timer 1.C/T2 selects F (timer operation) or external pin T2 (counter operation) as the timer clock input ...
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... Programmable Clock- Output AT89C51ID2 36 Figure 12. Auto-Reload Mode Up/Down Counter (DCEN = 1) F CLK PERIPH : 6 In the clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock gen- erator (See Figure 13). The input clock increments TL2 at frequency F timer repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2 ...
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... Figure 13. Clock-Out Mode C/ FCLK PERIPH T2 T2EX AT89C51ID2 TR2 T2CON 2 TL2 TH (8-bit) (8-bit) RCAP2H RCAP2L (8-bit) (8-bit) Toggle Q D T2OE T2MOD EXF2 T2CON EXEN2 T2CON OVER- FLOW TIMER 2 INTERRUPT 37 ...
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... Registers AT89C51ID2 38 Table 25. T2CON Register T2CON - Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 overflow Flag 7 TF2 Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1 ...
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... Timer 2 Output Enable bit 1 T2OE Cleared to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output. Down Counter Enable bit 0 DCEN Cleared to disable Timer 2 as up/down counter. Set to enable Timer 2 as up/down counter. Reset Value = XXXX XX00b Not bit addressable AT89C51ID2 T2OE 0 DCEN 39 ...
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... The Timer 0 overflow • The input on the ECI pin (P1.2) AT89C51ID2 ÷ CLK PERIPH ÷ CLK PERIPH External I/O Pin P1.2 / ECI P1.3 / CEX0 P1 ...
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... Figure 14. PCA Timer/Counter Fclk periph /6 Fclk periph / 2 T0 OVF P1.2 Idle AT89C51ID2 41 CH CIDL WDTE CPS1 CPS0 CF CR CCF4 CCF3 CCF2 CCF1 CCF0 To PCA modules overflow bit up counter CMOD ECF 0xD9 CCON 0xD8 4289C–8051–11/05 ...
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... Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this bit. • Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software. AT89C51ID2 ...
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... AT89C51ID2 43 • Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software. Table 28. CCON Register CCON - PCA Counter Control Register (D8h) ...
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... CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. • The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. AT89C51ID2 CCON 0xD8 To Interrupt priority decoder IEN0 ...
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... AT89C51ID2 45 Table 29 shows the CCAPMn settings for the various PCA functions. Table 29. CCAPMn Registers (n = 0-4) CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh) CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh) CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh) CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh) ...
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... CCAP4H - PCA Module 4 Compare/Capture Control Register High (0FEh Bit Bit Number Mnemonic Description PCA Module n Compare/Capture Control 7-0 - CCAPnH Value Reset Value = 0000 0000b Not bit addressable AT89C51ID2 TOGn PWMm ECCFn Module Function Operation 16-bit capture by a positive-edge trigger on CEXn 16-bit capture by a negative trigger ...
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... AT89C51ID2 47 Table 32. CCAPnL Registers (n = 0-4) CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh) CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh) CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh) CCAP3L - PCA Module 3 Compare/Capture Control Register Low (0EDh) CCAP4L - PCA Module 4 Compare/Capture Control Register Low (0EEh) ...
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... CCAPMn register. The PCA timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (See Figure 17). AT89C51ID2 CCON 0xD8 ...
Page 49
... Figure 17. PCA Compare Mode and PCA Watchdog Timer Write to CCAPnL Reset Write t o CCAPnH Enable 1 0 High Speed Output Mode AT89C51ID2 49 CF CCF4 CR CCAPnH CCAPnL Match 16 bit comparator CH CL PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CIDL WDTE Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit. Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’ ...
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... CCAPLn SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode. AT89C51ID2 CCON 0xD8 PCA IT ...
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... PCA Watchdog Timer AT89C51ID2 51 Figure 19. PCA PWM Mode Overflow Enable ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge ...
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... Serial I/O Port Framing Error Detection 4289C–8051–11/05 The serial I/O port in the AT89C51ID2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3) ...
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... Automatic Address Recognition Given Address AT89C51ID2 53 Figure 22. UART Timings in Modes 2 and 3 RXD D0 D1 Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 The automatic address recognition feature is enabled when the multiprocessor commu- nication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame ...
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... On reset, the SADDR and SADEN registers are initialized to 00h the given and broadcast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. AT89C51ID2 54 ...
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... Registers Baud Rate Selection for UART for Mode 1 and 3 AT89C51ID2 55 Table 35. SADEN Register SADEN - Slave Address Mask Register (B9h Reset Value = 0000 0000b Not bit addressable Table 36. SADDR Register SADDR - Slave Address Register (A9h Reset Value = 0000 0000b Not bit addressable The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers ...
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... BRG 1 BRL SPD • The baud rate for UART is token by formula: ⋅ F SMOD1 2 PER Baud_Rate = ⋅ 32 ⋅ (256 -BRL) (1-SPD) 6 ⋅ F SMOD1 2 PER BRL = 256 - ⋅ 32 ⋅ Baud_Rate (1-SPD) 6 AT89C51ID2 TBCK RBCK Clock Source (BDRCON) UART Timer Timer Timer Timer INT_BRG 1 ...
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... AT89C51ID2 57 Table 38. SCON Register SCON - Serial Control Register (98h FE/SM0 SM1 SM2 Bit Bit Number Mnemonic Description Framing Error bit (SMOD0=1 ) Clear to reset the error state, not cleared by a valid stop bit. FE Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit. ...
Page 58
... Table 41. SADEN Register SADEN - Slave Address Mask Register for UART (B9h Reset Value = 0000 0000b Table 42. SADDR Register SADDR - Slave Address Register for UART (A9h Reset Value = 0000 0000b AT89C51ID2 F = 24MHz OSC Error (%) BRL 1.23 243 1.23 230 1.23 217 1.23 204 0 ...
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... AT89C51ID2 59 Table 43. SBUF Register SBUF - Serial Buffer Register for UART (99h Reset Value = XXXX XXXXb Table 44. BRL Register BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah Reset Value = 0000 0000b 4289C–8051–11/05 ...
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... Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. 0 CP/RL2# Cleared to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. Reset Value = 0000 0000b Bit addressable AT89C51ID2 TCLK EXEN2 TR2 C/T2# Description 1 ...
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... AT89C51ID2 61 Table 46. PCON Register PCON - Power Control Register (87h SMOD1 SMOD0 - Bit Bit Number Mnemonic Serial port Mode bit 1 for UART 7 SMOD1 Set to select double baud rate in mode Serial port Mode bit 0 for UART 6 SMOD0 Cleared to select SM0 bit in SCON register. ...
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... Set to select the FAST Baud Rate Generator. Baud Rate Source select bit in Mode 0 for UART Cleared to select F 0 SRC mode). Set to select the internal Baud Rate Generator for UARTs in mode 0. Reset Value = XXX0 0000b Not bit addressablef AT89C51ID2 BRR TBCK RBCK SPD /12 as the Baud Rate Generator (F ...
Page 63
... Individual Enable 4289C–8051–11/05 The AT89C51ID2 has a total of 10 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard interrupt and the PCA global interrupt. These interrupts are shown in Figure 25 ...
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... Registers AT89C51ID2 64 The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located at address 0043H and Keyboard interrupt vector is located at address 004BH. All other vectors addresses are the same as standard C52 devices. Table 48. Priority Level Bit Values IPH low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’ ...
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... Timer 0 overflow interrupt Enable bit 1 ET0 Cleared to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. External interrupt 0 Enable bit 0 EX0 Cleared to disable external interrupt 0. Set to enable external interrupt 0. Reset Value = 0000 0000b Bit addressable AT89C51ID2 ET1 EX1 ET0 1 0 EX0 65 ...
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... AT89C51ID2 66 Table 50. IPL0 Register IPL0 - Interrupt Priority Register (B8h PPCL PT2L Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA interrupt Priority bit 6 PPCL Refer to PPCH for priority level. Timer 2 overflow interrupt Priority bit ...
Page 67
... PX1HPX1LPriority Level 0 0Lowest 2 PX1H 1Highest Timer 0 overflow interrupt Priority High bit PT0HPT0LPriority Level 0 0Lowest 1 PT0H 1Highest External interrupt 0 Priority High bit PX0H PX0LPriority Level 0 0Lowest 0 PX0H 1Highest Reset Value = X000 0000b Not bit addressable AT89C51ID2 PSH PT1H PX1H PT0H 1 0 PX0H 67 ...
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... AT89C51ID2 68 Table 52. IEN1 Register IEN1 - Interrupt Enable Register (B1h Bit Bit Number Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved SPI interrupt Enable bit Cleared to disable SPI interrupt. 2 ESPI Set to enable SPI interrupt. TWI interrupt Enable bit 1 ETWI Cleared to disable TWI interrupt. ...
Page 69
... The value read from this bit is indeterminate. Do not set this bit. SPI interrupt Priority bit 2 SPIL Refer to SPIH for priority level. TWI interrupt Priority bit 1 TWIL Refer to TWIH for priority level. Keyboard interrupt Priority bit 0 KBDL Refer to KBDH for priority level. Reset Value = XXXX X000b Bit addressable AT89C51ID2 SPIL TWIL 0 KBDL 69 ...
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... AT89C51ID2 70 Table 55. IPH1 Register IPH1 - Interrupt Priority High Register (B3h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Reserved 5 - The value read from this bit is indeterminate. Do not set this bit. ...
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... Table 56. Interrupt Sources and Vector Addresses Number Polling Priority Interrupt Source Keyboard AT89C51ID2 Interrupt Request Reset INT0 IE0 Timer 0 TF0 INT1 IE1 Timer 1 IF1 UART RI+TI Timer 2 TF2+EXF2 PCA CF + CCFn (n = 0-4) KBDIT TWI TWIIT SPI SPIIT Vector Address 0000h 0003h 000Bh ...
Page 72
... Idle mode. The contents of the status of the Port pins during Idle mode is detailed in Table 57. To enter Idle mode, set the IDL bit in PCON register (see Table 58). The AT89C51ID2 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed ...
Page 73
... Take care, however, that VDD is not reduced until Power-Down mode is invoked. To enter Power-Down mode, set PD bit in PCON register. The AT89C51ID2 enters the Power-Down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed. ...
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... Idle (external Floating Data code) Power- Down(inter Data Data nal code) Power- Down Floating Data (external code) AT89C51ID2 , but does not affect the internal SFRs Port 2 Port 3 Port 4 High High High Data Data Data Data Data Data Data Data Data ...
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... Registers AT89C51ID2 75 Table 58. PCON Register PCON (S87:h) Power configuration Register Bit Bit Number Mnemonic Description Reserved 7-5 - The value read from these bits is indeterminate. Do not set these bits. Power-Off Flag Cleared to recognize next reset type. 4 POF Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software ...
Page 76
... Interrupt Power Reduction Mode 4289C–8051–11/05 The AT89C51ID2 implements a keyboard interface allowing the connection matrix keyboard based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1 and allow to exit from idle and power down modes. ...
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... Registers AT89C51ID2 77 Table 59. KBF Register KBF-Keyboard Flag Register (9Eh KBF7 KBF6 KBF5 Bit Bit Number Mnemonic Description Keyboard line 7 flag Set by hardware when the Port line 7 detects a programmed level. It generates a 7 KBF7 Keyboard interrupt request if the KBKBIE. 7 bit in KBIE register is set. ...
Page 78
... Cleared to enable standard I/O pin. Set to enable KBF. 1 bit in KBF register to generate an interrupt request. Keyboard line 0 Enable bit 0 KBE0 Cleared to enable standard I/O pin. Set to enable KBF. 0 bit in KBF register to generate an interrupt request. Reset Value= 0000 0000b AT89C51ID2 KBE4 KBE3 KBE2 KBE1 ...
Page 79
... AT89C51ID2 79 Table 61. KBLS Register KBLS-Keyboard Level Selector Register (9Ch KBLS7 KBLS6 KBLS5 Bit Bit Number Mnemonic Description Keyboard line 7 Level Selection bit 7 KBLS7 Cleared to enable a low level detection on Port line 7. Set to enable a high level detection on Port line 7. Keyboard line 6 Level Selection bit ...
Page 80
... Kbit/s in standard mode. Various communication configuration can be designed using this bus. Figure 29 shows a typical 2-wire bus configuration. All the devices connected to the bus can be master and slave. Figure 29. 2-wire Bus Configuration device1 device2 device3 SCL SDA AT89C51ID2 ... deviceN 80 ...
Page 81
... Figure 30. Block Diagram Input Filter SDA PI2.1 Output Stage Input Filter SCL PI2.0 Output Stage AT89C51ID2 81 SSADR Address Register Comparator SSDAT Shift Register Arbitration & Sink Logic Timing & Control logic Serial clock generator Timer 1 overflow Control Register SSCON Status Status ...
Page 82
... Slave transmitter • Slave receiver Data transfer in each mode of operation is shown in Table to Table 70 and Figure 32. to Figure 35.. These figures contain the following abbreviations START condition R : Read bit (high level at SDA) AT89C51ID2 acknowledgement acknowledgement signal from receiver signal from receiver 1 2 3-8 ...
Page 83
... Master Transmitter Mode Master Receiver Mode AT89C51ID2 83 W: Write bit (low level at SDA) A: Acknowledge bit (low level at SDA) A: Not acknowledge bit (high level at SDA) Data: 8-bit data byte P : STOP condition In Figure 32 to Figure 35, circles are used to indicate when the serial interrupt flag is set. ...
Page 84
... In the slave transmitter mode, a number of data bytes are transmitted to a master receiver (Figure 35). Data transfer is initialized as in the slave receiver mode. When SSADR and SSCON have been initialized, the TWI module waits until it is addressed by AT89C51ID2 ...
Page 85
... Miscellaneous States Notes AT89C51ID2 85 its own slave address followed by the data direction bit which must be at logic 1 (R) for TWI to operate in the slave transmitter mode. After its own slave address and the R bit have been received, the serial interrupt flag is set and a valid status code can be read from SSCS ...
Page 86
... Data 18h A P 20h Other master continues 38h Other master A continues 68h 78h B0h Data A n AT89C51ID2 A P 28h S SLA 10h A P 30h Other master continues 38h To corresponding states in slave mode Any number of data bytes and their associated acknowledge bits This number (contained in SSCS) corresponds ...
Page 87
... No SSDAT action Write data byte No SSDAT action Data byte has been 30h transmitted; NOT ACK No SSDAT action has been received No SSDAT action No SSDAT action Arbitration lost in 38h SLA+W or data bytes No SSDAT action AT89C51ID2 87 Application software response To SSCON SSSTA SSSTO SSI SSAA ...
Page 88
... continues 38h Other master A continues 68h 78h B0h Any number of data bytes and their associated Data A acknowledge bits This number (contained in SSCS) corresponds defined state of the 2-wire bus AT89C51ID2 A P Data 58h S SLA R 10h W MT Other master A continues 38h To corresponding states in slave mode ...
Page 89
... Data byte has been 50h received; ACK has been returned Read data byte Read data byte Data byte has been Read data byte 58h received; NOT ACK has been returned Read data byte AT89C51ID2 89 Application software response To SSCON SSSTA SSSTO SSI SSAA ...
Page 90
... S SLA W A 60h A 68h General Call A 70h A 78h Any number of data bytes and their associated Data A acknowledge bits This number (contained in SSCS) corresponds defined state of the 2-wire bus AT89C51ID2 Data Data A A 80h 80h 88h Data A Data A 90h 90h ...
Page 91
... Previously addressed with own SLA+W; data has been 88h received; NOT ACK has been returned Previously addressed with general call; data has been 90h received; ACK has been returned AT89C51ID2 91 Application Software Response To/from SSDAT To SSCON STA STO SI No SSDAT action or X ...
Page 92
... No SSDAT action SSDAT action AT89C51ID2 AA Next Action Taken By 2-wire Software Switched to the not addressed slave mode; no recognition of own SLA or GCA 0 Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if 1 GC=logic 1 Switched to the not addressed slave mode; no recognition of own SLA or GCA ...
Page 93
... Arbitration lost in SLA+R/W as master; own SLA+R has been B0h received; ACK has been returned Data byte in SSDAT has been B8h transmitted; NOT ACK has been received AT89C51ID2 93 A Data SLA R A8h A B0h Any number of data bytes and their associated Data ...
Page 94
... SI= 0 Bus error due SSDAT 00h illegal START or action STOP condition AT89C51ID2 SI AA Next Action Taken By 2-wire Software Switched to the not addressed slave mode; no recognition of own SLA or GCA 0 0 Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if ...
Page 95
... Registers AT89C51ID2 95 Table 71. SSCON Register SSCON - Synchronous Serial Control register (93h CR2 SSIE STA Bit Bit Number Mnemonic Description Control Rate bit 2 7 CR2 See Table 65. Synchronous Serial Interface Enable bit 6 SSIE Clear to disable the TWI module. Set to enable the TWI module. ...
Page 96
... Table 75. SSADR (096h) - Synchronus Serial Address Register (read/write Table 76. SSADR Register - Reset value = FEh Bit Bit Number Mnemonic Description 7 A7 Slave Address bit Slave Address bit Slave Address bit Slave Address bit Slave Address bit Slave Address bit Slave Address bit 1 AT89C51ID2 SC1 SC0 ...
Page 97
... AT89C51ID2 97 Bit Bit Number Mnemonic Description General Call bit 0 GC Clear to disable the general call address recognition. Set to enable the general call address recognition. 4289C–8051–11/05 ...
Page 98
... MOSI and MISO lines driven by the Master for eight clock cycles which allows to exchange one Byte on the serial lines. Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any message for a Slave obvious that only one Master (SS high level) can AT89C51ID2 Slave 1 Slave 3 Slave 2 ...
Page 99
... Baud Rate AT89C51ID2 99 drive the network. The Master may select each Slave device by software through port pins (Figure 37). To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the Master for a transmission Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and SCK (see Error conditions) ...
Page 100
... When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock (Figure 38). AT89C51ID2 Internal Bus SPDAT Shift Register ...
Page 101
... Master Mode Slave Mode Transmission Formats AT89C51ID2 101 Figure 38. Full-Duplex Master-Slave Interconnection MISO 8-bit Shift register MOSI SPI SCK Clock Generator SS VDD Master MCU The SPI operates in Master mode when the Master bit, MSTR is set. Only one Master SPI device can initiate transmissions. Software begins the trans- mission from a Master SPI Module by writing to the Serial Peripheral Data Register (SPDAT) ...
Page 102
... MOSI pin on the first SCK edge. Therefore, the Slave uses the first SCK edge as a start transmission signal. The SS pin can remain low between transmis- sions (Figure 41). This format may be preffered in systems having only one Master and only one Slave driving the MISO data line. AT89C51ID2 ...
Page 103
... Write Collision (WCOL) Overrun Condition SS Error Flag (SSERR) Interrupts AT89C51ID2 103 The following flags in the SPSTA signal SPI error conditions: Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. MODF is set to warn that there may be a multi-master conflict for system control ...
Page 104
... Set to have the SCK set to ’1’ in idle low. Clock Phase Cleared to have the data sampled when the SCK leaves the idle 2 CPHA state (see CPOL). Set to have the data sampled when the SCK returns to idle state (see CPOL). AT89C51ID2 SPI CPU Interrupt Request Table MSTR ...
Page 105
... Serial Peripheral Status Register (SPSTA) AT89C51ID2 105 Bit Number Bit Mnemonic Description SPR2 SPR1 SPR0 1 1 Reset Value = 0001 0100b Not bit addressable The Serial Peripheral Status Register contains flags to signal the following conditions: • Data transfer complete • Write collision • ...
Page 106
... However, special care should be taken when writing to them while a transmission is on-going: • Do not change SPR2, SPR1 and SPR0 • Do not change CPHA and CPOL • Do not change MSTR • Clearing SPEN would immediately disable the peripheral • Writing to the SPDAT will cause an overflow. AT89C51ID2 Table ...
Page 107
... Table 82. WDTRST Register WDTRST - Watchdog Reset Register (0A6h Reset Value = XXXX XXXXb Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence. AT89C51ID2 , where T CLK PERIPH 7 counter has been added to extend the Time-out = 12MHz. To manage this feature, refer to OSCA ...
Page 108
... WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the AT89C51ID2 while in Idle mode, the user should always set up a timer that will periodi- cally exit Idle, service the WDT, and re-enter Idle mode. ...
Page 109
... Pull ALE low while the device is in reset (RST high) and PSEN is high. • Hold ALE low as RST is deactivated. While the AT89C51ID2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 84 shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied. ...
Page 110
... Cleared by hardware when reset occurs. Set to enter power-down mode. Idle mode bit 0 IDL Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. Reset Value = 00X1 0000b Not bit addressable AT89C51ID2 switch-on. A warm start reset occurs while POF GF1 GF0 rises from 0 to its nominal voltage. Can also be set by ...
Page 111
... EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that the EEPROM segment is not available for reading or writing. • The end of programming is indicated by a hardware clear of the EEBUSY flag. Figure 43 represents the optimal write sequence to the on-chip EEPROM data memory. AT89C51ID2 111 ...
Page 112
... AT89C51ID2 112 Figure 43. Recommended EEPROM Data Write Sequence EEPROM Data Write EEPROM Data Mapping EECON = 02h (EEE=1) Exec: MOVX @DPTR, A EECON = 00h (EEE=0) Sequence EEBusy Cleared? Save & Disable IT EA= 0 Data Write DPTR= Address ACC= Data EEPROM Mapping Restore IT Last Byte to Load? 4289C– ...
Page 113
... Set bit EEE of EECON register • Execute a MOVX A, @DPTR • Clear bit EEE of EECON register • Restore interrupts. Figure 44. Recommended EEPROM Data Read Sequence AT89C51ID2 EEPROM Data Read Sequence EEBusy Cleared? Save & Disable IT EA= 0 EEPROM Data Mapping EECON = 02h (EEE=1) ...
Page 114
... Registers AT89C51ID2 114 Table 86. EECON Register EECON (0D2h) EEPROM Control Register Bit Bit Number Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Enable EEPROM Space bit Set to map the EEPROM space during MOVX instructions (Write or Read to ...
Page 115
... XRAM selected. ALE Output bit Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1 mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is used. Reset Value = XX00 10’HSB. XRAM’0b Not bit addressable AT89C51ID2 XRS2 XRS1 XRS0 EXTRAM 1 ...
Page 116
... EPROM programmer. The parallel programming method used by these devices is similar to that used by EPROM 87C51 but it is not identical and the commercially available programmers need to have support for the AT89C51ID2. The bootloader and the Application Programming Interface (API) routines are located in the BOOT ROM. ...
Page 117
... Software registers are in a special page of the Flash memory which can be accessed through the API or with the parallel programming modes. This page, called "Extra Flash Memory", is not in the internal Flash program memory addressing space. The only hardware register of the AT89C51ID2 is called Hardware Security Byte (HSB). Table 88. Hardware Security Byte (HSB ...
Page 118
... These registers are in the "Extra Flash Memory" part of the Flash memory. This block is also called "XAF" or eXtra Array Flash. They are accessed in the following ways: • Commands issued by the parallel memory programmer. • Commands issued by the ISP software. • Calls of API issued by the application software. Several software registers described in Table 90. AT89C51ID2 118 ...
Page 119
... The two lock bits provide different levels of protection for the on-chip code and data, when programmed as shown to Table 93. Default value Description FCh 101x 1011b 0FFh FFh 58h ATMEL D7h C51 X2, Electrically Erasable ECh AT89C51ID2 64KB AT89C51ID2 64KB, Revision EFh LB1 0 LB0 4289C–8051–11/05 ...
Page 120
... X: do not care WARNING: Security level 2 and 3 should only be programmed after Flash and code verification. AT89C51ID2 parts are delivered in standard with the ISP rom bootloader. After ISP or parallel programming, the possible contents of the Flash memory are sum- marized on the figure below: ...
Page 121
... Acronyms AT89C51ID2 121 The bootloader manages a communication according to a specific defined protocol to provide the whole access and service on Flash memory. Furthermore, all accesses and routines can be called from the user application. Figure 46. Diagram Context Description ...
Page 122
... Results are returned in the registers. The pur- pose on this process is to translate the registers values into internal Flash Memory Management. • Flash Memory Management This process manages low level access to flash memory (performs read and write access). AT89C51ID2 User Application User Call Management (API ) 122 ...
Page 123
... Bootloader Functionality Introduction Figure 48. Hardware conditions typical sequence during power-on. AT89C51ID2 123 The bootloader can be activated by two means: Hardware conditions or regular boot process. The Hardware conditions ( PSEN = 0) during the Reset# falling edge force the on-chip bootloader execution. This allows an application to be built that will normally execute the end user’ ...
Page 124
... The Software Boot Vector contains the high address of custumer bootloader stored in the application. SBV = FCh (default value custumer bootloader in user Flash. SBV Note: The costumer bootloader is called by JMP [SBV]00h instruction. AT89C51ID2 Purpose 124 ...
Page 125
... Boot Process Figure 49. Bootloader Process PC=0000h USER APPLICATION AT89C51ID2 125 RESET If BLJB=0 then ENBOOT bit (AUXR1) is set else ENBOOT bit (AUXR1) is cleared Yes (PSEN = and ALE =1 or not connected) FCON = 00h Hardware condition? FCON = F0h BLJB=1 BLJB!= 0 ENBOOT=0 ? BLJB=0 ENBOOT=1 F800h ...
Page 126
... Reclen field to and including the last byte of the Data/Info field. Therefore, the sum of all the ASCII pairs in a record after converting to binary, from the Reclen field to and including the Checksum field, is zero. AT89C51ID2 Data Load Record ...
Page 127
... Bootloader info Read only access allowed Erase block Full chip erase Blank Check AT89C51ID2 127 The SSB protects any Flash access from ISP command. The command "Program Software Security bit" can only write a higher priority level. There are three levels of security: • ...
Page 128
... BSB = FFh • SBV = FCh • SSB = FFh and finally erase the Software Security Bits The Full Chip Erase does not affect the bootloader. When a checksum error is detected send ‘X’ followed with CR&LF. AT89C51ID2 128 ...
Page 129
... This information is then used to pro- gram the baud rate in terms of timer counts based on the oscillator frequency. The ISP feature requires that an initial character (an uppercase U) be sent to the AT89C51ID2 to establish the baud rate. Table show the autobaud capability. ...
Page 130
... Echo analysis 4289C–8051–11/05 2 2.4576 All commands are sent using the same flow. Each frame sent by the host is echoed by the bootloader. ":" ":" AT89C51ID2 3.6864 Bootloader If (not received ":") Else Sends echo and start reception Gets frame, and sends back ec ...
Page 131
... Wait Checksum Error COMMAND ABORTED OR Wait Security Error COMMAND ABORTED Wait COMMAND_OK COMMAND FINISHED Example AT89C51ID2 131 This flow is common to the following frames: • Flash / Eeprom Programming Data Frame • EOF or Atmel Frame (only Programming Atmel Frame) • Config Byte Programming Data Frame • ...
Page 132
... CR LF BOOTLOADER Blank Check with checksum error HOST : 05 0000 04 0000 7FFF 01 70 BOOTLOADER : 05 0000 04 0000 7FFF AT89C51ID2 Bootloader Wait Blank Check Command Checksum error Send Checksum error Flash blank Send COMMAND_OK Send first Address ...
Page 133
... COMMAND ABORTED Wait Display Data All data read COMMAND FINISHED Note: The maximum size of block is 400h. To read more than 400h bytes, the Host must send a new command. AT89C51ID2 133 Display Command ’X’ & CR & LF Send Checksum Error ’L’ & CR & LF ...
Page 134
... Reading Frame • EOF Frame/ Atmel Frame (only reading Atmel Frame) Read Command ’X’ & CR & LF ’L’ & CR & LF ’value’ & ’.’ & CR & LF AT89C51ID2 (16 data) (16 data data) Bootloader Wait Read Command Checksum error Send Checksum error ...
Page 135
... Example AT89C51ID2 135 Read function (read SBV) HOST : 02 0000 BOOTLOADER : 02 0000 Value . CR LF Atmel Read function (read Bootloader version) HOST : 02 0000 BOOTLOADER : 02 0000 Value . CR LF 4289C–8051–11/05 ...
Page 136
... Data[0:1] = start address Data [2:3] = end address Display Function Data[4] = 00h -> Display data Data[4] = 01h -> Blank check Data[4] = 02h -> Display EEPROMk AT89C51ID2 data[1] Command Effect Program Nb Data Byte. Bootloader will accept up to 128 (80h) data bytes. The data bytes should be 128 byte page flash boundary ...
Page 137
... Table 96. ISP Commands Summary (Continued) Command 05h 07h AT89C51ID2 137 Command Name data[0] 00h Read Function 07h 0Bh 0Eh 0Fh Program EEPROM data data[1] Command Effect 00h Manufacturer Id 01h Device Id #1 02h Device Id #2 03h Device Id #3 00h Read SSB 01h ...
Page 138
... DPH = 00h DPL = 11h 0000h XXh 0001h XXh 0000h XXh 0001h XXh 0002h XXh AT89C51ID2 Returned Value Command Effect Read Manufacturer identifier Id ACC = Device Id 1 Read Device identifier 1 ACC = Device Id 2 Read Device identifier 2 ACC = Device Id 3 Read Device identifier 3 Erase block 0 ...
Page 139
... READ HSB 0Bh XXh READ BOOT ID1 0Eh XXh READ BOOT ID2 0Eh XXh READ BOOT VERSION 0Fh XXh AT89C51ID2 139 DPTR0 DPTR1 Returned Value Address of Address in the first byte ACC = 0: DONE XRAM of the to program in first data to the Flash ...
Page 140
... CC device reliability. (2) Power dissipation is based on the maximum allow- able die temperature and the thermal resistance of the package. Min Typ -0.5 0 0 ( 1 AT89C51ID2 Max Unit Test Conditions 4. 100 μ ...
Page 141
... Under steady state (non-transient) conditions, I Maximum I per port pin Maximum I per 8-bit port: OL Port Ports 1, 2 and Maximum total I for all output pins exceeds the test condition than the listed test conditions. AT89C51ID2 141 Min Typ 1 (5) 50 ...
Page 142
... Test Condition, Power-down Mode RST EA (NC) XTAL2 XTAL1 V SS Figure 60. Clock Signal Waveform for I V -0.5V CC 0.45V T CHCL T CLCH AT89C51ID2 All other pins are disconnected All other pins are disconnected. CC All other pins are disconnected. Tests in Active and Idle Modes CC 0.7V CC 0.2V -0 CLCH = T = 5ns. ...
Page 143
... Explanation of the AC Symbols External Program Memory Characteristics AT89C51ID2 143 Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for ...
Page 144
... Symbol Type Clock T Min LHLL T Min AVLL T Min LLAX T Max LLIV T Min LLPL T Min PLPH T Max PLIV T Min x PXIX T Max PXIZ T Max AVIV T Max x PLAZ AT89C51ID2 -L Max Min Max parameter for X parameter for X2 Clock -M range -L range Units ns ns ...
Page 145
... External Program Memory Read Cycle ALE PSEN PORT 0 INSTR IN ADDRESS PORT 2 OR SFR-P2 External Data Memory Characteristics AT89C51ID2 145 LHLL LLIV T LLPL T PLPH T LLAX T PLIV T T AVLL TPLAZ PXIX A0-A7 INSTR IN T AVIV ADDRESS A8-A15 Table 101. Symbol Description Symbol Parameter ...
Page 146
... T Max RHDZ T Max LLDV T Max 4 AVDV T Min 1 LLWL T Max 1 LLWL T Min AVWL T Min 0 QVWX T Min 3 QVWH T Min 0 WHQX T Max x RLAZ T Min 0 WHLH T Max 0 WHLH AT89C51ID2 -L Max Min 125 125 155 160 105 155 parameter for X parameter for -M range -L range Max Units ...
Page 147
... External Data Memory Write Cycle ALE PSEN WR PORT 0 ADDRESS PORT 2 OR SFR-P2 External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Serial Port Timing - Shift Register Mode AT89C51ID2 147 T LLWL T QVWX T LLAX A0-A7 T AVWL ADDRESS A8-A15 OR SFR P2 T LLDV T LLWL T AVDV T ...
Page 148
... Min x XHDX T Max XHDV XLXL T XHQX XHDX T XHDV VALID VALID VALID V -0.5V CC 0.7V CC 0.2V -0.1 0.45V CC T CHCL AT89C51ID2 -L Max Min 300 200 30 0 117 X Parameter For X Parameter For -M Range -L Range 133 133 SET TI VALID VALID VALID VALID SET RI T CHCX T T ...
Page 149
... AC Testing Input/Output Waveforms Float Waveforms Clock Waveforms AT89C51ID2 149 V -0.5V CC INPUT/OUTPUT 0.45V AC inputs during testing are driven at V Timing measurement are made 0. 0.1V OL For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V ≥ ...
Page 150
... FLOAT INDICATES ADDRESS TRANSITIONS DPL OR Rt OUT FLOAT INDICATES DPH OR P2 SFR TO PCH TRANSITION DPL OR Rt OUT DATA OUT INDICATES DPH OR P2 SFR TO PCH TRANSITION OLD DATA NEW DATA P0 PINS SAMPLED P1, P2, P3 PINS SAMPLED RXD SAMPLED AT89C51ID2 STATE3 STATE4 STATE5 DATA ...
Page 151
... Change Log for 4289A - 09/03 to 4289B - 12/03 4289B - 12/03 to 4289C - 11/05 4289C–8051–11/05 Table 107. Possible Order Entries Supply Part Number Voltage AT89C51ID2-SLSIM AT89C51ID2-RLTIM 2.7V-5.5V AT89C51ID2-SLSUM AT89C51ID2-RLTUM 1. Improvement of explanations throughout the document. 1. Added ‘Industrial & Green” product versions. AT89C51ID2 Temperature ...
Page 152
... Packaging Information PLCC44 AT89C51ID2 152 4289C–8051–11/05 ...
Page 153
... VQFP44 4289C–8051–11/05 AT89C51ID2 153 ...
Page 154
... Table of Contents AT89C51ID2 i Features................................................................................................. 1 Description ............................................................................................ 1 Block Diagram....................................................................................... 3 SFR Mapping......................................................................................... 4 Pin Configurations.............................................................................. 10 Oscillators ........................................................................................... 14 Overview............................................................................................................. 14 Registers............................................................................................................. 14 Functional Block Diagram................................................................................... 17 Operating Modes ................................................................................................ 17 Design Considerations........................................................................................ 19 Timer 0: Clock Inputs.......................................................................................... 20 Enhanced Features............................................................................. 21 X2 Feature .......................................................................................................... 21 Dual Data Pointer Register DPTR...................................................... 25 Expanded RAM (XRAM) ..................................................................... 28 Registers............................................................................................................. 30 Reset .................................................................................................... 31 Introduction ......................................................................................................... 31 Reset Input ......................................................................................................... 31 Reset Output ...
Page 155
... Functional Description ...................................................................................... 100 Hardware Watchdog Timer .............................................................. 107 Using the WDT ................................................................................................. 107 WDT During Power Down and Idle................................................................... 108 ONCE(TM) Mode (ON Chip Emulation) ........................................... 109 Power-off Flag................................................................................... 110 EEPROM Data Memory..................................................................... 111 Write Data......................................................................................................... 111 Read Data......................................................................................................... 113 Registers........................................................................................................... 114 Reduced EMI Mode........................................................................... 115 AT89C51ID2 ii ...
Page 156
... AT89C51ID2 iii Flash Memory.................................................................................... 116 Features............................................................................................................ 116 Flash Programming and Erasure...................................................................... 116 Flash Registers and Memory Map.................................................................... 117 Flash Memory Status........................................................................................ 120 Memory Organization ....................................................................................... 120 Bootloader Architecture .................................................................................... 121 ISP Protocol Description................................................................................... 126 Functional Description ...................................................................................... 127 Flow Description ............................................................................................... 129 API Call Description.......................................................................................... 138 Electrical Characteristics ...
Page 157
... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...